Method of manufacturing semiconductor device

ABSTRACT

To provide a semiconductor device with low parasitic capacitance, a semiconductor device with low power consumption, a semiconductor device having favorable frequency characteristics, or a highly integrated semiconductor device. In a method of manufacturing a semiconductor device including a semiconductor, a first conductor, a second conductor, a third conductor, and an insulator, the semiconductor includes a first region in contact with the first conductor, a second region in contact with the second conductor, and a third region in contact with the insulator. The third conductor includes a region in which the third conductor and the semiconductor overlap with each other with the insulator interposed therebetween. The first region, the second region, and the third region do not overlap with each other. The first conductor is selectively grown over the first region, and the second conductor is selectively grown over the second region.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an object, a method, or a manufacturing method. Furthermore, the present invention relates to a process, a machine, manufacture, or a composition of matter. In particular, the present invention relates to, for example, a semiconductor, a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, or a processor. The present invention relates to a method of manufacturing a semiconductor, a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, or a processor. The present invention relates to a method of driving a semiconductor device, a display device, a light-emitting device, a lighting device, a power storage device, a memory device, or a processor.

In this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A display device, a light-emitting device, a lighting device, an electro-optical device, a semiconductor circuit, and an electronic device include a semiconductor device in some cases.

2. Description of the Related Art

A technique for forming a transistor by using a semiconductor over a substrate having an insulating surface has attracted attention. The transistor is applied to a wide range of semiconductor devices such as an integrated circuit and a display device. Silicon is known as a semiconductor applicable to a transistor.

As silicon used as a semiconductor of a transistor, any of amorphous silicon, polycrystalline silicon, single crystal silicon, and the like is used depending on the purpose. For example, in the case of a transistor included in a large display device, it is preferable to use amorphous silicon, which can be used to form a film on a large substrate with the established technique. On the other hand, in the case of a transistor included in a high-performance display device where a driver circuit and a pixel circuit are formed over the same substrate, it is preferable to use polycrystalline silicon, which can be used to form a transistor having a high field-effect mobility. Furthermore, in the case of a transistor included in an integrated circuit or the like, it is preferable to use single crystal silicon which provides a much higher field-effect mobility. As a method of forming a film using polycrystalline silicon, high-temperature heat treatment or laser light treatment that is performed on amorphous silicon has been known.

In recent years, an oxide semiconductor has attracted attention. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a semiconductor of a transistor in a large display device. Because a transistor including an oxide semiconductor has high field-effect mobility, a high-performance display device in which, for example, a driver circuit and a pixel circuit are formed over the same substrate can be obtained. In addition, there is an advantage that capital investment can be reduced because part of production equipment for a transistor including amorphous silicon can be retrofitted and utilized.

A transistor including an oxide semiconductor is known to have extremely small leakage current in an off state. For example, a low-power CPU and the like utilizing the leakage current of the transistor including an oxide semiconductor is disclosed (see Patent Document 1). In application to integrated circuits such as CPUs, preferably, a transistor including an oxide semiconductor is reduced in size and the degree of integration is increased.

When the degree of integration is increased in a semiconductor device, parasitic capacitance formed by overlap between wirings, electrodes, and the like might have a non-negligible effect. According to Patent Document 2, even with an offset region, a disclosed transistor achieves excellent electrical characteristics by electron injection from a conductor electrode to a semiconductor. By the technique disclosed in Patent Document 2, the parasitic capacitance formed by overlap between wirings, electrodes, and the like can be reduced.

Patent Document 3 discloses that a transistor having high field-effect mobility can be obtained by a well potential formed using an active layer formed of a semiconductor (see Patent Document 3).

REFERENCES Patent Documents [Patent Document 1] Japanese Published Patent Application No. 2012-257187 [Patent Document 2] Japanese Published Patent Application No. 2011-22507 [Patent Document 3] Japanese Published Patent Application No. 2012-59860 SUMMARY OF THE INVENTION

An object is to provide a transistor with low parasitic capacitance. Another object is to provide a transistor having favorable switching characteristics. Another object is to provide a transistor having low current in an off state. Another object is to provide a transistor having high current in an on state. Another object is to provide a semiconductor device including the transistor. Another object is to provide a semiconductor device with low parasitic capacitance. Another object is to provide a semiconductor device with low power consumption. Another object is to provide a semiconductor device having favorable frequency characteristics. Another object is to provide a highly integrated semiconductor device. Another object is to provide a durable semiconductor device. Another object is to provide a novel semiconductor device.

Note that the descriptions of these objects do not disturb the existence of other objects. In one embodiment of the present invention, there is no need to achieve all the objects. Other objects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

(1)

One embodiment of the present invention is a method of manufacturing a semiconductor device including a semiconductor, a first conductor, a second conductor, a third conductor, and an insulator. The semiconductor includes a first region in contact with the first conductor, a second region in contact with the second conductor, and a third region in contact with the insulator. The third conductor includes a region in which the third conductor and the semiconductor overlap with each other with the insulator interposed between the third conductor and the semiconductor. The first region and the third region do not overlap with each other, and the second region and the third region do not overlap with each other. The first conductor is selectively grown over the first region, and the second conductor is selectively grown over the second region.

(2)

One embodiment of the present invention is a method of manufacturing a semiconductor device, including the steps of: forming a semiconductor over a first insulator; forming a second insulator over the semiconductor; forming a first conductor over the second insulator; etching part of the first conductor to form a second conductor including a region overlapping with the semiconductor with the second insulator interposed between the region and the semiconductor; etching part of the second insulator to form a third insulator in a region overlapping with the second conductor; adding an impurity to the semiconductor with the second conductor as a mask; forming a fourth insulator over the semiconductor and the second conductor; anisotropically etching the fourth insulator to form a fifth insulator including a region in contact with a side surface of the second conductor; etching an exposed region of the second insulator at the same time as the anisotropic etching; etching an exposed region of the first insulator at the same time as the anisotropic etching to form a region having a small thickness in the first insulator; and selectively growing a conductor over an exposed region of a region to which the impurity is added in the semiconductor.

(3)

One embodiment of the present invention is a method of manufacturing a semiconductor device, including the steps of: forming a semiconductor over a first insulator; forming a second insulator over the semiconductor; forming a first conductor over the second insulator; etching part of the first conductor to form a second conductor including a region overlapping with the semiconductor with the second insulator interposed between the region and the semiconductor; forming a third insulator over the second insulator and the second conductor; forming a fourth insulator over the third insulator after adding an impurity to the semiconductor with the second conductor as a mask; anisotropically etching the third insulator and the fourth insulator to form a fifth insulator including a region in contact with a side surface of the second conductor; etching an exposed region of the second insulator at the same time as the anisotropic etching; etching an exposed region of the first insulator at the same time as the anisotropic etching to form a region having a small thickness in the first insulator; and selectively growing a conductor over an exposed region of a region to which the impurity is added in the semiconductor.

(4)

One embodiment of the present invention is the method of manufacturing a semiconductor device, which is described in (2) or (3) and in which the impurity is added by an ion implantation method.

(5)

One embodiment of the present invention is the method of manufacturing a semiconductor device, which is described in (2) or (3) and in which the impurity is added by an ion implantation method using a cluster ion.

(6)

One embodiment of the present invention is the method of manufacturing a semiconductor device, which is described in any one of (2) to (5) and in which the impurity includes silicon and the conductor is selectively grown by a chemical vapor deposition method using a gas including tungsten.

(7)

One embodiment of the present invention is the method of manufacturing a semiconductor device, which is described in (6) and in which the gas including tungsten includes a tungsten hexafluoride gas or a monosilane gas.

(8)

One embodiment of the present invention is the method of manufacturing a semiconductor device, which is described in any one of (2) to (5) and in which the impurity includes titanium and the conductor is selectively grown by a chemical vapor deposition method using a gas including aluminum.

(9)

One embodiment of the present invention is the method of manufacturing a semiconductor device, which is described in (8) and in which the gas including aluminum includes a diethylaluminium hydride gas.

A transistor with low parasitic capacitance can be provided. A transistor having favorable switching characteristics can be provided. A transistor having low current in an off state can be provided. A transistor having high current in an on state can be provided. A semiconductor device including the transistor can be provided. A semiconductor device with low parasitic capacitance can be provided. A semiconductor device with low power consumption can be provided. A semiconductor device having favorable frequency characteristics can be provided. A highly integrated semiconductor device can be provided. A durable semiconductor device can be provided. A novel semiconductor device can be provided.

Note that the description of the effects does not disturb the existence of other effects. One embodiment of the present invention does not necessarily achieve all the effects. Other effects will be apparent from and can be derived from the description of the specification, the drawings, the claims, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS

In the accompanying drawings:

FIGS. 1A to 1D are cross-sectional views illustrating selective growth of a conductor according to one embodiment of the present invention;

FIGS. 2A and 2B are cross-sectional views illustrating a method of manufacturing a transistor according to one embodiment of the present invention;

FIGS. 3A and 3B are cross-sectional views illustrating the method of manufacturing a transistor according to one embodiment of the present invention;

FIGS. 4A and 4B are cross-sectional views illustrating the method of manufacturing a transistor according to one embodiment of the present invention;

FIGS. 5A and 5B are cross-sectional views illustrating the method of manufacturing a transistor according to one embodiment of the present invention;

FIGS. 6A and 6B are a cross-sectional view and a top view illustrating a transistor according to one embodiment of the present invention;

FIGS. 7A and 7B are cross-sectional views each illustrating a transistor according to one embodiment of the present invention;

FIGS. 8A and 8B are cross-sectional views each illustrating a transistor according to one embodiment of the present invention;

FIGS. 9A and 9B are cross-sectional views illustrating a method of manufacturing a transistor according to one embodiment of the present invention;

FIGS. 10A and 10B are cross-sectional views illustrating the method of manufacturing a transistor according to one embodiment of the present invention;

FIGS. 11A and 11B are cross-sectional views illustrating the method of manufacturing a transistor according to one embodiment of the present invention;

FIGS. 12A and 12B are cross-sectional views illustrating the method of manufacturing a transistor according to one embodiment of the present invention;

FIGS. 13A and 13B are a cross-sectional view and a top view illustrating a transistor according to one embodiment of the present invention;

FIGS. 14A and 14B are cross-sectional views each illustrating a transistor according to one embodiment of the present invention;

FIGS. 15A and 15B are cross-sectional views each illustrating a transistor according to one embodiment of the present invention;

FIGS. 16A and 16B are cross-sectional views each illustrating a semiconductor device according to one embodiment of the present invention;

FIGS. 17A and 17B are each a circuit diagram of a semiconductor device according to one embodiment of the present invention;

FIGS. 18A and 18B are each a circuit diagram of a memory device according to one embodiment of the present invention;

FIG. 19 is a block diagram of an RF tag according to one embodiment of the present invention;

FIGS. 20A to 20F illustrate application examples of an RF tag according to one embodiment of the present invention;

FIG. 21 is a block diagram illustrating a CPU according to one embodiment of the present invention;

FIG. 22 is a circuit diagram of a memory element according to one embodiment of the present invention;

FIGS. 23A to 23C are a top view and circuit diagrams of a display device according to one embodiment of the present invention;

FIG. 24 illustrates a display module according to one embodiment of the present invention;

FIGS. 25A to 25F illustrate electronic devices according to one embodiment of the present invention;

FIGS. 26A1 to 26C2 illustrate an electronic device according to one embodiment of the present invention;

FIGS. 27A to 27D are Cs-corrected high-resolution TEM images of a cross section of a CAAC-OS and a cross-sectional schematic view of a CAAC-OS;

FIGS. 28A to 28D are Cs-corrected high-resolution TEM images of a plane of a CAAC-OS;

FIGS. 29A to 29C show structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD;

FIGS. 30A and 30B show electron diffraction patterns of a CAAC-OS;

FIG. 31 shows a change in crystal part of an In—Ga—Zn oxide induced by electron irradiation;

FIGS. 32A to 32C are a cross-sectional view of stacked semiconductor layers and diagrams showing a band structure;

FIGS. 33A and 33B are cross-sectional views each illustrating a transistor according to one embodiment of the present invention; and

FIGS. 34A and 34B are cross-sectional views each illustrating a transistor according to one embodiment of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. However, the present invention is not limited to the description below, and it is easily understood by those skilled in the art that modes and details disclosed herein can be modified in various ways. Furthermore, the present invention is not construed as being limited to description of the embodiments. In describing structures of the present invention with reference to the drawings, common reference numerals are used for the same portions in different drawings. Note that the same hatched pattern is applied to similar parts, and the similar parts are not especially denoted by reference numerals in some cases.

Note that the size, the thickness of films (layers), or regions in diagrams may be exaggerated for clarity.

A voltage usually refers to a potential difference between a given potential and a reference potential (e.g., a source potential or a ground potential (GND)). A voltage can be referred to as a potential and vice versa.

Note that the ordinal numbers such as “first” and “second” in this specification are used for the sake of convenience and do not denote the order of steps or the stacking order of layers. Therefore, for example, the term “first” can be replaced with the term “second”, “third”, or the like as appropriate. In addition, the ordinal numbers in this specification and the like are not necessarily the same as the ordinal numbers used to specify one embodiment of the present invention.

Note that a “semiconductor” includes characteristics of an “insulator” in some cases when the conductivity is sufficiently low, for example. Furthermore, a “semiconductor” and an “insulator” cannot be strictly distinguished from each other in some cases because a border between the “semiconductor” and the “insulator” is not clear. Accordingly, a “semiconductor” in this specification can be called an “insulator” in some cases. Similarly, an “insulator” in this specification can be called a “semiconductor” in some cases.

Furthermore, a “semiconductor” includes characteristics of a “conductor” in some cases when the conductivity is sufficiently high, for example. Furthermore, a “semiconductor” and a “conductor” cannot be strictly distinguished from each other in some cases because a border between the “semiconductor” and the “conductor” is not clear. Accordingly, a “semiconductor” in this specification can be called a “conductor” in some cases. Similarly, a “conductor” in this specification can be called a “semiconductor” in some cases.

Note that an impurity in a semiconductor refers to, for example, elements other than the main components of a semiconductor. For example, an element the concentration of which is less than 0.1 atomic % is an impurity. When an impurity is contained, the density of states (DOS) may be formed in a semiconductor, the carrier mobility may be decreased, or the crystallinity may be decreased, for example. When the semiconductor is an oxide semiconductor, examples of an impurity which changes the characteristics of the semiconductor include Group 1 elements, Group 2 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components; specifically, there are hydrogen (including water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen, for example. When the semiconductor is an oxide semiconductor, oxygen vacancies may be formed by entry of impurities such as hydrogen, for example. Furthermore, when the semiconductor is silicon, examples of an impurity which changes the characteristics of the semiconductor include oxygen, Group 1 elements except hydrogen, Group 2 elements, Group 13 elements, and Group 15 elements.

In embodiments described below, the case where the semiconductor is an oxide semiconductor is described; however, the present invention is not limited thereto. For example, as the semiconductor, silicon, germanium, or the like which has a polycrystalline structure, a single crystal structure, or the like may be used. Alternatively, a semiconductor having distortion such as distorted silicon may be used. Alternatively, as the semiconductor, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like which can be used for a HEMT may be used. By using any of these semiconductors, a transistor capable of high speed operation can be obtained.

In this specification, the phrase “A has a region with a concentration B” includes, for example, the cases where “the concentration in the entire region in a region of A in the depth direction is B”, “the average concentration in a region of A in the depth direction is B”, “the median value of the concentration in a region of A in the depth direction is B”, “the maximum value of the concentration in a region of A in the depth direction is B”, “the minimum value of the concentration in a region of A in the depth direction is B”, “a convergence value of the concentration in a region of A in the depth direction is B”, and “a concentration in a region of A in which a probable value is obtained in measurement is B”.

In this specification, the phrase “A has a region with a size B, a length B, a thickness B, a width B, or a distance B” includes, for example, “the size, the length, the thickness, the width, or the distance of the entire region in a region of A is B”, “the average value of the size, the length, the thickness, the width, or the distance of a region of A is B”, “the median value of the size, the length, the thickness, the width, or the distance of a region of A is B”, “the maximum value of the size, the length, the thickness, the width, or the distance of a region of A is B”, “the minimum value of the size, the length, the thickness, the width, or the distance of a region of A is B”, “a convergence value of the size, the length, the thickness, the width, or the distance of a region of A is B”, and “the size, the length, the thickness, the width, or the distance of a region of A in which a probable value is obtained in measurement is B”.

In this specification, an insulator, a semiconductor, a conductor, or the like can be formed by a sputtering method, a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like unless otherwise specified.

The CVD method can include a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD) method using heat, and the like. Moreover, the CVD method can include a metal CVD (MCVD) method and a metal organic CVD (MOCVD) method depending on a source gas.

By using the plasma enhanced CVD method, a high-quality film can be formed at a relatively low temperature. By using the thermal CVD method, in which plasma is not used, a film can be formed with few defects because damage caused by plasma does not occur.

When the CVD method is used, the composition of a film to be formed can be controlled with a flow rate ratio of the source gases. For example, by the MCVD method and the MOCVD method, a film with a certain composition can be formed depending on a flow rate ratio of the source gases. Moreover, with the MCVD method and the MOCVD method, by changing the flow rate ratio of the source gases while forming the film, a film whose composition is continuously changed can be formed. In the case where the film is formed while changing the flow rate ratio of the source gases, as compared to the case where the film is formed using a plurality of deposition chambers, time taken for the film formation can be reduced because time taken for transfer and pressure adjustment is not needed. Thus, transistors can be manufactured with improved productivity.

Note that the channel length refers to, for example, a distance between a source (a source region or a source electrode) and a drain (a drain region or a drain electrode) in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other or a region where a channel is formed in a top view of the transistor. In one transistor, channel lengths in all regions are not necessarily the same. In other words, the channel length of one transistor is not limited to one value in some cases. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width refers to, for example, the length of a portion where a source and a drain face each other in a region where a semiconductor (or a portion where a current flows in a semiconductor when a transistor is on) and a gate electrode overlap with each other, or a region where a channel is formed, in a top view. In one transistor, channel widths in all regions do not necessarily have the same value. In other words, a channel width of one transistor is not fixed to one value in some cases. Therefore, in this specification, a channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on transistor structures, a channel width in a region where a channel is formed actually (hereinafter referred to as an effective channel width) is different from a channel width shown in a top view of a transistor (hereinafter referred to as an apparent channel width) in some cases. For example, in a transistor having a three-dimensional structure, an effective channel width is greater than an apparent channel width shown in a top view of the transistor, and its influence cannot be ignored in some cases. For example, in a miniaturized transistor having a three-dimensional structure, the proportion of a channel region formed in a side surface of a semiconductor is higher than the proportion of a channel region formed in a top surface of the semiconductor in some cases. In that case, an effective channel width obtained when a channel is actually formed is greater than an apparent channel width shown in the top view.

In a transistor having a three-dimensional structure, an effective channel width is difficult to measure in some cases. For example, to estimate an effective channel width from a design value, it is necessary to assume that the shape of a semiconductor is known. Therefore, in the case where the shape of a semiconductor is not known accurately, it is difficult to measure an effective channel width accurately.

Therefore, in this specification, in a top view of a transistor, an apparent channel width that is a length of a portion where a source and a drain face each other in a region where a semiconductor and a gate electrode overlap with each other is referred to as a surrounded channel width (SCW) in some cases. Furthermore, in this specification, in the case where the term “channel width” is simply used, it may denote a surrounded channel width and an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width in some cases. Note that the values of a channel length, a channel width, an effective channel width, an apparent channel width, a surrounded channel width, and the like can be determined by obtaining and analyzing a cross-sectional TEM image and the like.

Note that in the case where field-effect mobility, a current value per channel width, and the like of a transistor are obtained by calculation, a surrounded channel width may be used for the calculation. In that case, a value different from one in the case where an effective channel width is used for the calculation is obtained in some cases.

<Selective Growth of Conductor>

Selective growth of a conductor according to one embodiment of the present invention is described below using FIGS. 1A to 1D.

First, a mask 102 is formed over part of a sample 100.

Next, treatment for adding an impurity 150 is performed (see FIG. 1A). The impurity 150 can be added by an ion doping method, an ion implantation method, or the like. In this specification, the term ion doping method refers to addition of ions that are not mass-separated. The term ion implantation method refers to addition of ions that are mass-separated.

The impurity 150 can be changed as appropriate depending on the kind of conductor to be selectively grown. As the impurity 150, for example, an ion including silicon or titanium can be added. Note that a cluster-like ion (also referred to as a cluster ion) may be used as the impurity 150. The use of a cluster ion allows the impurity 150 to be added to a shallow region (the vicinity of the top surface) of the sample 100, which might be favorable in some cases. Note that as the cluster ion including silicon, a Si_(n) ion (n is an integer greater than or equal to 2 and less than or equal to 60, preferably 6 or 10) and the like can be given. As the cluster ion including titanium, Ti_(n) (n is an integer greater than or equal to 2 and less than or equal to 16) and the like can be given.

The addition of the impurity 150 is not necessarily performed by an ion doping method or an ion implantation method. For example, the impurity 150 may be added as follows: a film containing the impurity 150 is formed over the sample 100, and the sample 100 is then subjected to plasma treatment, an ion doping method, or an ion implantation method, so that the impurity 150 is added by a knock-on effect (also referred to as a mixing effect). In this case, a residue of the film into which the impurity has not been added may be removed. For the removal, a wet etching method, a dry etching method, or the like can be used.

The impurity 150 is added to only a region in which the mask 102 is not provided, and a region 104 is formed on the top surface of part of the sample 100 (see FIG. 1B). The region 104 is a region in which the concentration of the impurity 150 is high. The region 104 includes a region in which the concentration of one of the elements of the impurity 150 is greater than or equal to 1×10¹⁹ atoms/cm³, for example.

Next, the mask 102 is removed (see FIG. 1C). A wet etching method, a dry etching method, or the like can be used to remove the mask 102. At this time, conditions are determined such that at least part of the region 104 remains.

Next, a conductor 106 is selectively grown over the region 104. A method of selectively growing the conductor 106 is not particularly limited, but for example, a CVD method is preferably used. The case where the conductor 106 is selectively grown by an MCVD method or an MOCVD method is particularly described.

For the selective growth of the conductor 106 over the region 104, the impurity 150 and a source gas of the conductor 106 can be combined as appropriate. For example, when the region 104 contains silicon as the impurity 150, a tungsten hexafluoride (WF₆) gas, or a WF₆ gas and a monosilane (SiH₄) gas is/are used as the source gas of the conductor 106, so that tungsten can be selectively grown.

Specifically, tungsten can be selectively grown over the region 104 by a Si reduction reaction represented by the following equation (1).

2WF₆(g)+3Si(s)=2W(s)+3SiF₄(g)  (1)

In the Si reduction reaction, silicon etching occurs while tungsten is generated. Hence, the reaction terminates when added silicon is lost.

When such a method is used for selective growth of tungsten, for example, the thickness of tungsten can be controlled by the addition amount of silicon or by the depth at which silicon is added because silicon in the region 104 is lost as the selective growth proceeds. Note that a method similar to this might allow the thickness of the conductor 106 to be controlled in some cases, even with different combinations of the impurity 150 and the source gas.

To render tungsten thicker, another conductor can be selectively grown over tungsten after silicon in the region 104 is lost. For example, use of a WF₆ gas and a hydrogen (H₂) gas as the source gas enables tungsten to grow further thicker.

Specifically, tungsten can be selectively grown by a H₂ reduction reaction represented by the following equation (2).

WF₆(g)+3H₂(g)=W(s)+6HF(g)  (2)

It is known that activation energy of the H₂ reduction reaction is 0.71 eV and the rate of the entire reaction is determined by the adsorption and dissociation of H₂ molecules on the tungsten surface. In the H₂ reduction reaction, the growth rate is increased at a relatively high temperature. For the selective growth of tungsten, for example, the surface temperature of the sample 100 can be greater than or equal to 300° C. and less than or equal to 600° C., greater than or equal to 350° C. and less than or equal to 550° C., or greater than or equal to 400° C. and less than or equal to 500° C.

Note that in the Si reduction reaction represented by the equation (1), tungsten is less likely to be generated on a silicon oxide surface and a silicon oxynitride surface each having a thickness of 2 nm or more, and therefore tungsten can be selectively grown over the region 104.

A reaction of a WF₆ gas on a silicon oxide surface is represented by the following equation (3).

2WF₆(g)+SiO₂(s)=2WOF₄(g)+SiF₄(g)  (3)

Thus, on the silicon oxide surface, only etching of silicon oxide occurs by reaction with the WF₆ gas and the reaction product is all exhausted as a gas.

Alternatively, tungsten can be selectively grown over the region 104 by a SiH₄ reduction reaction represented by the following equation (4).

2WF₆(g)+3SiH₄(g)=2W(s)+3SiF₄(g)+6H₂(g)  (4)

When WF₆ and SiH₄ are present in the vicinity of silicon, the probability of SiH₄ being adsorbed is low and the probability of reaction of WF₆ and silicon is high. Hence, the SiH₄ reduction reaction occurs on a tungsten surface precipitated by silicon reduction. The SiH₄ reduction reaction occurs at a temperature greater than or equal to 180° C. and less than or equal to 450° C.; therefore for the selective growth of tungsten, for example, the surface temperature of the sample 100 can be greater than or equal to 180° C. and less than or equal to 450° C., greater than or equal to 190° C. and less than or equal to 380° C., or greater than or equal to 200° C. and less than or equal to 320° C.

A reduction reaction similar to the above can be caused by using a disilane (Si₂H₆) gas or the like instead of a SiH₄ gas. For example, a Si₂H₆ reduction reaction occurs at a temperature greater than or equal to 80° C. and less than or equal to 240° C.; therefore for the selective growth of tungsten, for example, the surface temperature of the sample 100 can be greater than or equal to 80° C. and less than or equal to 240° C., greater than or equal to 100° C. and less than or equal to 210° C., or greater than or equal to 120° C. and less than or equal to 180° C. Alternatively, a B₂H₆ reduction reaction using a diborane (B₂H₆) gas instead of a SiH₄ gas may be employed for the selective growth of tungsten.

Note that in a reduction reaction using silane such as the SiH₄ reduction reaction, silicon is likely to remain in tungsten. In addition, the silicon concentration in tungsten increases as the temperature rises. For example, when the surface temperature of the sample 100 is approximately 400° C., W₅Si₃ is generated in some cases.

The mask 102 may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. When the mask 102 contains an impurity, the range of selection of the conductor 106 can be widened. As the impurity, for example, phosphorus or the like can be used.

For example, when the region 104 contains titanium as the impurity 150 and a diethylaluminium hydride [(CH₃)₂AlH] gas is used as the source gas of the conductor 106, aluminum can be selectively grown.

The above-described combination of the impurity 150 and the source gas of the conductor 106 is an example, and one embodiment of the present invention is not limited to the combination.

Using the above-described method of selectively growing the conductor, a semiconductor device with reduced parasitic capacitance or the like can be manufactured.

<Transistor Structure 1>

A transistor and a method of manufacturing the transistor according to one embodiment of the present invention are described below. Note that the method of manufacturing the transistor is described using cross sections along the channel length direction (A1-A2 cross section) and the channel width direction (A3-A4 cross section).

First, a substrate 400 is prepared.

As the substrate 400, an insulator substrate, a semiconductor substrate, or a conductor substrate may be used, for example. As the insulator substrate, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (e.g., an yttria-stabilized zirconia substrate), or a resin substrate is used, for example. As the semiconductor substrate, a semiconductor substrate of silicon, germanium, or the like or a compound semiconductor substrate of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide, gallium oxide, or the like is used, for example. A semiconductor substrate in which an insulator region is provided in the above semiconductor substrate, e.g., a silicon on insulator (SOI) substrate or the like is used. As the conductor substrate, a graphite substrate, a metal substrate, an alloy substrate, a conductive resin substrate, or the like is used. A substrate including a metal nitride, a substrate including a metal oxide, or the like is used. An insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, a conductor substrate provided with a semiconductor or an insulator, or the like is used. Alternatively, any of these substrates over which an element is provided may be used. As the element provided over the substrate, a capacitor, a resistor, a switching element, a light-emitting element, a memory element, or the like is used.

Alternatively, a flexible substrate may be used as the substrate 400. As the substrate 400, a sheet, a film, or foil containing a fiber may be used. The substrate 400 may have elasticity. The substrate 400 may have a property of returning to its original shape when bending or pulling is stopped. Alternatively, the substrate 400 may have a property of not returning to its original shape. The thickness of the substrate 400 is, for example, greater than or equal to 5 μm and less than or equal to 700 μm, preferably greater than or equal to 10 μm and less than or equal to 500 μm, more preferably greater than or equal to 15 μm and less than or equal to 300 μm. When the substrate 400 has a small thickness, the weight of the semiconductor device can be reduced. When the substrate 400 has a small thickness, even in the case of using glass or the like, the substrate 400 may have elasticity or a property of returning to its original shape when bending or pulling is stopped. Therefore, an impact applied to the semiconductor device over the substrate 400, which is caused by dropping or the like, can be reduced. That is, a durable semiconductor device can be provided.

For the substrate 400 which is a flexible substrate, metal, an alloy, resin, glass, or fiber thereof can be used, for example. The flexible substrate 400 preferably has a lower coefficient of linear expansion because deformation due to an environment is suppressed. The flexible substrate 400 is formed using, for example, a material whose coefficient of linear expansion is lower than or equal to 1×10⁻³/K, lower than or equal to 5×10⁻⁵/K, or lower than or equal to 1×10⁻⁵/K. Examples of the resin include polyester, polyolefin, polyamide (e.g., nylon or aramid), polyimide, polycarbonate, and acrylic. In particular, aramid is preferably used for the flexible substrate 400 because of its low coefficient of linear expansion.

As a method of providing a transistor over a flexible substrate, there is a method in which a transistor is formed over a non-flexible substrate and then the transistor is separated and transferred to a flexible substrate. In that case, a separation layer is preferably provided over the substrate 400 which is a non-flexible substrate.

Next, an insulator 402 is formed (see FIG. 2A). The insulator 402 may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Note that the insulator 402 may include an insulator containing nitrogen such as silicon nitride oxide or silicon nitride.

The insulator 402 may have a function of preventing diffusion of impurities from the substrate 400.

The insulator 402 may be an insulator containing excess oxygen.

The insulator containing excess oxygen means an insulator from which oxygen is released by heat treatment, for example. Silicon oxide containing excess oxygen means silicon oxide which can release oxygen by heat treatment or the like, for example. Therefore, the insulator 402 is an insulator in which oxygen can be moved.

Here, an insulator from which oxygen is released by heat treatment may release oxygen, the amount of which is higher than or equal to 1×10¹⁸ atoms/cm³, higher than or equal to 1×10¹⁹ atoms/cm³, or higher than or equal to 1×10²⁰ atoms/cm³ (converted into the number of oxygen atoms) in TDS analysis in the range of a surface temperature of 100° C. to 700° C. or 100° C. to 500° C.

Here, the method of measuring the amount of released oxygen using TDS analysis is described below.

The total amount of released gas from a measurement sample in TDS analysis is proportional to the integral value of the ion intensity of the released gas. Then, comparison with a reference sample is made, whereby the total amount of released gas can be calculated.

For example, the number of released oxygen molecules (No₂) from a measurement sample can be calculated according to the following equation using the TDS results of a silicon substrate containing hydrogen at a predetermined density, which is a reference sample, and the TDS results of the measurement sample. Here, all gases having a mass number of 32 which are obtained in the TDS analysis are assumed to originate from an oxygen molecule. Note that CH₃OH, which is a gas having the mass number of 32, is not taken into consideration because it is unlikely to be present. Furthermore, an oxygen molecule including an oxygen atom having a mass number of 17 or 18 which is an isotope of an oxygen atom is also not taken into consideration because the proportion of such a molecule in the natural world is minimal.

N_(O2)═N_(H2)/S_(H2)×S_(O2)×α

The value N_(H2) is obtained by conversion of the number of hydrogen molecules desorbed from the reference sample into densities. The value S_(H2) is the integral value of ion intensity in the case where the reference sample is subjected to the TDS analysis. Here, the reference value of the reference sample is set to N_(H2)/S_(H2). The value S_(O2) is the integral value of ion intensity when the measurement sample is analyzed by TDS. The value α is a coefficient affecting the ion intensity in the TDS analysis. Refer to Japanese Published Patent Application No. H6-275697 for details of the above equation. The amount of released oxygen was measured with a thermal desorption spectroscopy apparatus produced by ESCO Ltd., EMD-WA1000S/W using a silicon substrate containing hydrogen atoms at 1×10¹⁶ atoms/cm² as the reference sample.

Furthermore, in the TDS analysis, oxygen is partly detected as an oxygen atom. The ratio between oxygen molecules and oxygen atoms can be calculated from the ionization rate of the oxygen molecules. Note that, since the above a includes the ionization rate of the oxygen molecules, the amount of the released oxygen atoms can also be estimated through the evaluation of the amount of the released oxygen molecules.

Note that N_(O2) is the amount of the released oxygen molecules. The amount of released oxygen in the case of being converted into oxygen atoms is twice the amount of the released oxygen molecules.

Furthermore, the insulator from which oxygen is released by heat treatment may contain a peroxide radical. Specifically, the spin density attributed to the peroxide radical is greater than or equal to 5×10¹⁷ spins/cm³. Note that the insulator containing a peroxide radical may have an asymmetric signal with a g factor of approximately 2.01 in ESR.

The insulator containing excess oxygen may be formed using oxygen-excess silicon oxide (SiO_(X) (X>2)). In the oxygen-excess silicon oxide (SiO_(X) (X>2)), the number of oxygen atoms per unit volume is more than twice the number of silicon atoms per unit volume. The number of silicon atoms and the number of oxygen atoms per unit volume are measured by Rutherford backscattering spectrometry (RBS).

Next, a semiconductor 406 is formed (see FIG. 2B). The semiconductor 406 is formed in such a manner that the conductor to be the semiconductor 406 is formed and then partly etched.

The semiconductor 406 is an oxide semiconductor containing indium, for example. An oxide semiconductor can have high carrier mobility (electron mobility) by containing indium, for example. The semiconductor 406 preferably contains an element M. The element M is preferably aluminum, gallium, yttrium, tin, or the like. Other elements which can be used as the element M are boron, silicon, titanium, iron, nickel, germanium, yttrium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and the like. Note that two or more of the above elements may be used in combination as the element M. The element M is an element having high bonding energy with oxygen, for example. The element M is an element whose bonding energy with oxygen is higher than that of indium, for example. The element M is an element that can increase the energy gap of the oxide semiconductor, for example. Furthermore, the semiconductor 406 preferably contains zinc. When the oxide semiconductor contains zinc, the oxide semiconductor is easily crystallized, for example.

Note that the semiconductor 406 is not limited to the oxide semiconductor containing indium. The semiconductor 406 may be, for example, an oxide semiconductor which does not contain indium and contains zinc, an oxide semiconductor which does not contain indium and contains gallium, or an oxide semiconductor which does not contain indium and contains tin, e.g., a zinc tin oxide or a gallium tin oxide.

For the semiconductor 406, an oxide with a wide energy gap may be used. For example, the energy gap of the semiconductor 406 is greater than or equal to 2.5 eV and less than or equal to 4.2 eV, preferably greater than or equal to 2.8 eV and less than or equal to 3.8 eV, more preferably greater than or equal to 3 eV and less than or equal to 3.5 eV.

As factors of inhibiting electron movement are decreased, the on-state current of the transistor can be increased. For example, in the case where there is no factor of inhibiting electron movement, electrons are assumed to be efficiently moved. Electron movement is inhibited, for example, in the case where physical unevenness in a channel formation region is large.

To increase the on-state current of the transistor, for example, a root mean square (RMS) roughness with a measurement area of 1 μm×1 μm of a top surface or a bottom surface of the semiconductor 406 (a formation surface; here, the insulator 402) is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, still more preferably less than 0.4 nm. The average surface roughness (also referred to as Ra) with the measurement area of 1 μm×1 μm is less than 1 nm, preferably less than 0.6 nm, more preferably less than 0.5 nm, still more preferably less than 0.4 nm. The maximum difference (P−V) with the measurement area of 1 μm×1 μm is less than 10 nm, preferably less than 9 nm, more preferably less than 8 nm, still more preferably less than 7 nm. RMS roughness, Ra, and P−V can be measured using a scanning probe microscope SPA-500 manufactured by SII Nano Technology Inc.

Oxygen vacancies in an oxide semiconductor cause deterioration of electrical characteristics of the transistor in some cases. Accordingly, reducing oxygen vacancies in a channel formation region is important for the transistor to have stable electrical characteristics. On the other hand, in the case where an oxide semiconductor is used for a source region and a drain region of the transistor, oxygen vacancies can cause the oxide semiconductor to have lower resistance. Thus, in some cases, presence of oxygen vacancies is preferred to increase the on-state current of the transistor.

For example, in the case where the oxide semiconductor contains oxygen vacancies (also denoted by V_(O)), donor levels are formed by entry of hydrogen into sites of oxygen vacancies in some cases. A state in which hydrogen enters sites of oxygen vacancies are denoted by V_(O)H in the following description in some cases. Note that sites of oxygen vacancies become more stable by entry of oxygen than by entry of hydrogen. Thus, by supplying oxygen to the oxide semiconductor, V_(O)H can be reduced.

For example, a region in which the silicon concentration is less than 1×10¹⁹ atoms/cm³, preferably less than 5×10¹⁸ atoms/cm³, more preferably less than 2×10¹⁸ atoms/cm³ which is measured by secondary ion mass spectrometry (SIMS) is provided between semiconductor 406 and the insulator 402.

Note that when copper enters the oxide semiconductor, an electron trap might be generated. The electron trap might shift the threshold voltage of the transistor in the positive direction. Therefore, the concentration of copper on the surface of or in the semiconductor 406 is preferably as low as possible. For example, the semiconductor 406 preferably has a region in which the copper concentration is less than or equal to 1×10¹⁹ atoms/cm³, less than or equal to 5×10¹⁸ atoms/cm³, or less than or equal to 1×10¹⁸ atoms/cm³.

The structure of the oxide semiconductor is described below.

In this specification, the term “parallel” indicates that the angle formed between two straight lines is greater than or equal to −10° and less than or equal to 10°, and accordingly also includes the case where the angle is greater than or equal to −5° and less than or equal to 5°. The term “substantially parallel” indicates that the angle formed between two straight lines is greater than or equal to −30° and less than or equal to 30°. The term “perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 80° and less than or equal to 100°, and accordingly includes the case where the angle is greater than or equal to 85° and less than or equal to 95°. The term “substantially perpendicular” indicates that the angle formed between two straight lines is greater than or equal to 60° and less than or equal to 120°.

In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system.

<Structure of Oxide Semiconductor>

A structure of an oxide semiconductor is described below.

An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. Examples of a non-single-crystal oxide semiconductor include a c-axis aligned crystalline oxide semiconductor (CAAC-OS), a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor (nc-OS), an amorphous-like oxide semiconductor (a-like OS), and an amorphous oxide semiconductor.

From another perspective, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

It is known that an amorphous structure is generally defined as being metastable and unfixed, and being isotropic and having no non-uniform structure. In other words, an amorphous structure has a flexible bond angle and a short-range order but does not have a long-range order.

This means that an inherently stable oxide semiconductor cannot be regarded as a completely amorphous oxide semiconductor. Moreover, an oxide semiconductor that is not isotropic (e.g., an oxide semiconductor that has a periodic structure in a microscopic region) cannot be regarded as a completely amorphous oxide semiconductor. Note that an a-like OS has a periodic structure in a microscopic region, but at the same time has a void and has an unstable structure. For this reason, an a-like OS has physical properties similar to those of an amorphous oxide semiconductor.

<CAAC-OS>

First, a CAAC-OS is described.

A CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as pellets).

In a combined analysis image (also referred to as a high-resolution TEM image) of a bright-field image and a diffraction pattern of a CAAC-OS, which is obtained using a transmission electron microscope (TEM), a plurality of pellets can be observed. However, in the high-resolution TEM image, a boundary between pellets, that is, a grain boundary is not clearly observed. Thus, in the CAAC-OS, a reduction in electron mobility due to the grain boundary is less likely to occur.

A CAAC-OS observed with TEM is described below. FIG. 27A shows a high-resolution TEM image of a cross section of the CAAC-OS which is observed from a direction substantially parallel to the sample surface. The high-resolution TEM image is obtained with a spherical aberration corrector function. The high-resolution TEM image obtained with a spherical aberration corrector function is particularly referred to as a Cs-corrected high-resolution TEM image. The Cs-corrected high-resolution TEM image can be obtained with, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 27B is an enlarged Cs-corrected high-resolution TEM image of a region (1) in FIG. 27A. FIG. 27B shows that metal atoms are arranged in a layered manner in a pellet. Each metal atom layer has a configuration reflecting unevenness of a surface over which the CAAC-OS is formed (hereinafter, the surface is referred to as a formation surface) or a top surface of the CAAC-OS, and is arranged parallel to the formation surface or the top surface of the CAAC-OS.

As shown in FIG. 27B, the CAAC-OS has a characteristic atomic arrangement. The characteristic atomic arrangement is denoted by an auxiliary line in FIG. 27C. FIGS. 27B and 27C prove that the size of a pellet is approximately 1 nm to 3 nm, and the size of a space caused by tilt of the pellets is approximately 0.8 nm. Therefore, the pellet can also be referred to as a nanocrystal (nc). Furthermore, the CAAC-OS can also be referred to as an oxide semiconductor including c-axis aligned nanocrystals (CANC).

Here, according to the Cs-corrected high-resolution TEM images, the schematic arrangement of pellets 5100 of a CAAC-OS over a substrate 5120 is illustrated by such a structure in which bricks or blocks are stacked (see FIG. 27D). The part in which the pellets are tilted as observed in FIG. 27C corresponds to a region 5161 shown in FIG. 27D.

FIG. 28A shows a Cs-corrected high-resolution TEM image of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. FIGS. 28B, 28C, and 28D are enlarged Cs-corrected high-resolution TEM images of regions (1), (2), and (3) in FIG. 28A, respectively. FIGS. 28B, 28C, and 28D indicate that metal atoms are arranged in a triangular, quadrangular, or hexagonal configuration in a pellet. However, there is no regularity of arrangement of metal atoms between different pellets.

Next, a CAAC-OS analyzed by X-ray diffraction (XRD) is described. For example, when the structure of a CAAC-OS including an InGaZnO₄ crystal is analyzed by an out-of-plane method, a peak appears at a diffraction angle (2θ) of around 31° as shown in FIG. 29A. This peak is derived from the (009) plane of the InGaZnO₄ crystal, which indicates that crystals in the CAAC-OS have c-axis alignment, and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS.

Note that in structural analysis of the CAAC-OS by an out-of-plane method, another peak may appear when 2θ is around 36°, in addition to the peak at 2θ of around 31°. The peak at 2θ of around 36° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. It is preferable that in the CAAC-OS analyzed by an out-of-plane method, a peak appear when 2θ is around 31° and that a peak not appear when 2θ is around 36°.

On the other hand, in structural analysis of the CAAC-OS by an in-plane method in which an X-ray beam is incident on a sample in a direction substantially perpendicular to the c-axis, a peak appears when 2θ is around 56°. This peak is attributed to the (110) plane of the InGaZnO₄ crystal. In the case of the CAAC-OS, when analysis (φ scan) is performed with 2θ fixed at around 56° and with the sample rotated using a normal vector of the sample surface as an axis (φ axis), as shown in FIG. 29B, a peak is not clearly observed. In contrast, in the case of a single crystal oxide semiconductor of InGaZnO₄, when φ scan is performed with 2θ fixed at around 56°, as shown in FIG. 29C, six peaks which are derived from crystal planes equivalent to the (110) plane are observed. Accordingly, the structural analysis using XRD shows that the directions of a-axes and b-axes are irregularly oriented in the CAAC-OS.

Next, a CAAC-OS analyzed by electron diffraction is described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO₄ crystal in a direction parallel to the sample surface, a diffraction pattern (also referred to as a selected-area transmission electron diffraction pattern) shown in FIG. 30A might be obtained. In this diffraction pattern, spots derived from the (009) plane of an InGaZnO₄ crystal are included. Thus, the electron diffraction also indicates that pellets included in the CAAC-OS have c-axis alignment and that the c-axes are aligned in a direction substantially perpendicular to the formation surface or the top surface of the CAAC-OS. Meanwhile, FIG. 30B shows a diffraction pattern obtained in such a manner that an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. As shown in FIG. 30B, a ring-like diffraction pattern is observed. Thus, the electron diffraction also indicates that the a-axes and b-axes of the pellets included in the CAAC-OS do not have regular alignment. The first ring in FIG. 30B is considered to be derived from the (010) plane, the (100) plane, and the like of the InGaZnO₄ crystal. The second ring in FIG. 30B is considered to be derived from the (110) plane and the like.

As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Entry of impurities, formation of defects, or the like might decrease the crystallinity of an oxide semiconductor. This means that the CAAC-OS has small amounts of impurities and defects (e.g., oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element (specifically, silicon or the like) having higher strength of bonding to oxygen than a metal element included in an oxide semiconductor extracts oxygen from the oxide semiconductor, which results in disorder of the atomic arrangement and reduced crystallinity of the oxide semiconductor. A heavy metal such as iron or nickel, argon, carbon dioxide, or the like has a large atomic radius (or molecular radius), and thus disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

The characteristics of an oxide semiconductor having impurities or defects might be changed by light, heat, or the like. Impurities contained in the oxide semiconductor might serve as carrier traps or carrier generation sources, for example. Furthermore, oxygen vacancies in the oxide semiconductor serve as carrier traps or serve as carrier generation sources when hydrogen is captured therein.

The CAAC-OS having small amounts of impurities and oxygen vacancies is an oxide semiconductor with low carrier density (specifically, lower than 8×10¹¹/cm³, preferably lower than 1×10¹¹/cm³, further preferably lower than 1×10¹⁰/cm³, and is higher than or equal to 1×10⁻⁹/cm³). Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. A CAAC-OS has a low impurity concentration and a low density of defect states. Thus, the CAAC-OS can be referred to as an oxide semiconductor having stable characteristics.

<nc-OS>

Next, an nc-OS will be described.

An nc-OS has a region in which a crystal part is observed and a region in which a crystal part is not clearly observed in a high-resolution TEM image. In most cases, the size of a crystal part included in the nc-OS is greater than or equal to 1 nm and less than or equal to 10 nm, or greater than or equal to 1 nm and less than or equal to 3 nm. Note that an oxide semiconductor including a crystal part whose size is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. In a high-resolution TEM image of the nc-OS, for example, a grain boundary is not clearly observed in some cases. Note that there is a possibility that the origin of the nanocrystal is the same as that of a pellet in a CAAC-OS. Therefore, a crystal part of the nc-OS may be referred to as a pellet in the following description.

In the nc-OS, a microscopic region (for example, a region with a size greater than or equal to 1 nm and less than or equal to 10 nm, in particular, a region with a size greater than or equal to 1 nm and less than or equal to 3 nm) has a periodic atomic arrangement. There is no regularity of crystal orientation between different pellets in the nc-OS. Thus, the orientation of the whole film is not ordered. Accordingly, the nc-OS cannot be distinguished from an a-like OS or an amorphous oxide semiconductor, depending on an analysis method. For example, when the nc-OS is analyzed by an out-of-plane method using an X-ray beam having a diameter larger than the size of a pellet, a peak which shows a crystal plane does not appear. Furthermore, a diffraction pattern like a halo pattern is observed when the nc-OS is subjected to electron diffraction using an electron beam with a probe diameter (e.g., 50 nm or larger) that is larger than the size of a pellet. Meanwhile, spots appear in a nanobeam electron diffraction pattern of the nc-OS when an electron beam having a probe diameter close to or smaller than the size of a pellet is applied. Moreover, in a nanobeam electron diffraction pattern of the nc-OS, regions with high luminance in a circular (ring) pattern are shown in some cases. Also in a nanobeam electron diffraction pattern of the nc-OS, a plurality of spots is shown in a ring-like region in some cases.

Since there is no regularity of crystal orientation between the pellets (nanocrystals) as mentioned above, the nc-OS can also be referred to as an oxide semiconductor including random aligned nanocrystals (RANC) or an oxide semiconductor including non-aligned nanocrystals (NANC).

The nc-OS is an oxide semiconductor that has high regularity as compared with an amorphous oxide semiconductor. Therefore, the nc-OS is likely to have a lower density of defect states than an a-like OS and an amorphous oxide semiconductor. Note that there is no regularity of crystal orientation between different pellets in the nc-OS. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<A-Like OS>

An a-like OS has a structure intermediate between those of the nc-OS and the amorphous oxide semiconductor.

In a high-resolution TEM image of the a-like OS, a void may be observed. Furthermore, in the high-resolution TEM image, there are a region where a crystal part is clearly observed and a region where a crystal part is not observed.

The a-like OS has an unstable structure because it includes a void. To verify that an a-like OS has an unstable structure as compared with a CAAC-OS and an nc-OS, a change in structure caused by electron irradiation is described below.

An a-like OS (referred to as Sample A), an nc-OS (referred to as Sample B), and a CAAC-OS (referred to as Sample C) are prepared as samples subjected to electron irradiation. Each of the samples is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is obtained. The high-resolution cross-sectional TEM images show that all the samples have crystal parts.

Note that which part is regarded as a crystal part is determined as follows. It is known that a unit cell of an InGaZnO₄ crystal has a structure in which nine layers including three In—O layers and six Ga—Zn—O layers are stacked in the c-axis direction. The distance between the adjacent layers is equivalent to the lattice spacing on the (009) plane (also referred to as d value). The value is calculated to be 0.29 nm from crystal structural analysis. Accordingly, a portion where the lattice spacing between lattice fringes is greater than or equal to 0.28 nm and less than or equal to 0.30 nm is regarded as a crystal part of InGaZnO₄. Each of lattice fringes corresponds to the a-b plane of the InGaZnO₄ crystal.

FIG. 31 shows change in the average size of crystal parts (at 22 points to 45 points) in each sample. Note that the crystal part size corresponds to the length of a lattice fringe. FIG. 31 indicates that the crystal part size in the a-like OS increases with an increase in the cumulative electron dose. Specifically, as shown by (1) in FIG. 31, a crystal part of approximately 1.2 nm (also referred to as an initial nucleus) at the start of TEM observation grows to a size of approximately 2.6 nm at a cumulative electron dose of 4.2×10⁸ e⁻/nm². In contrast, the crystal part size in the nc-OS and the CAAC-OS shows little change from the start of electron irradiation to a cumulative electron dose of 4.2×10⁸ e⁻/nm². Specifically, as shown by (2) and (3) in FIG. 31, the average crystal sizes in an nc-OS and a CAAC-OS are approximately 1.4 nm and approximately 2.1 nm, respectively, regardless of the cumulative electron dose.

In this manner, growth of the crystal part in the a-like OS is induced by electron irradiation. In contrast, in the nc-OS and the CAAC-OS, growth of the crystal part is hardly induced by electron irradiation. Therefore, the a-like OS has an unstable structure as compared with the nc-OS and the CAAC-OS.

The a-like OS has a lower density than the nc-OS and the CAAC-OS because it includes a void. Specifically, the density of the a-like OS is higher than or equal to 78.6% and lower than 92.3% of the density of the single crystal oxide semiconductor having the same composition. The density of each of the nc-OS and the CAAC-OS is higher than or equal to 92.3% and lower than 100% of the density of the single crystal oxide semiconductor having the same composition. Note that it is difficult to deposit an oxide semiconductor having a density of lower than 78% of the density of the single crystal oxide semiconductor.

For example, in the case of an oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of single crystal InGaZnO₄ with a rhombohedral crystal structure is 6.357 g/cm³. Accordingly, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of the a-like OS is higher than or equal to 5.0 g/cm³ and lower than 5.9 g/cm³. For example, in the case of the oxide semiconductor having an atomic ratio of In:Ga:Zn=1:1:1, the density of each of the nc-OS and the CAAC-OS is higher than or equal to 5.9 g/cm³ and lower than 6.3 g/cm³.

Note that there is a possibility that an oxide semiconductor having a certain composition cannot exist in a single crystal structure. In that case, single crystal oxide semiconductors with different compositions are combined at an adequate ratio, which makes it possible to calculate density equivalent to that of a single crystal oxide semiconductor with the desired composition. The density of a single crystal oxide semiconductor having the desired composition can be calculated using a weighted average according to the combination ratio of the single crystal oxide semiconductors with different compositions. Note that it is preferable to use as few kinds of single crystal oxide semiconductors as possible to calculate the density.

As described above, oxide semiconductors have various structures and various properties. Note that an oxide semiconductor may be a stacked layer including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

The method of manufacturing the transistor is again described. An insulator 442 and a conductor 434 are next formed in this order (see FIG. 3A). The insulator 442 may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.

The conductor 434 may be formed to have, for example, a single-layer structure or a stacked-layer structure including a conductor containing one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound containing the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.

Next, the conductor 434 is partly etched, so that the conductor 404 is formed. Next, the insulator 442 is partly etched, so that an insulator 412 is formed (see FIG. 3B).

Next, treatment for adding an impurity 450 is performed (see FIG. 4A). For the impurity 450, refer to the description of the impurity 150.

The impurity 450 is added to a region in the vicinity of surfaces of the insulator 402, the semiconductor 406, the insulator 412, and the conductor 404. The region is referred to as a region 454 (see FIG. 4B). For the region 454, refer to the description of the region 104.

Next, an insulator is formed. Then, the insulator is anisotropically etched, so that an insulator 410 a in contact with a side surface of the conductor 404 and an insulator 410 b in contact with a side surface of the semiconductor 406 are formed. The insulators 410 a and 410 b may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The anisotropic etching can be performed by a dry etching method or the like. Note that the insulator 402 is half-etched during the anisotropic etching, and thus part of the insulator 402 is removed (see FIG. 5A).

Next, a conductor is selectively grown over an exposed region of the region 454. Consequently, conductors 416 a and 416 b are formed over the semiconductor 406. In addition, a conductor 416 c is formed over the conductor 404 (see FIG. 5B). For selective growth of the conductors 416 a, 416 b, and 416 c, refer to the description of the selective growth of the conductor 106.

Next, an insulator 418 is formed. The insulator 418 may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum.

Next, an opening reaching the conductor 416 a and an opening reaching the conductor 416 b are formed in the insulator 418, and conductors 405 a and 405 b are embedded in their respective openings. Note that the openings may penetrate the conductors 416 a and 416 b to reach the semiconductor 406. The conductors 405 a and 405 b may be formed to have, for example, a single-layer structure or a stacked-layer structure including a conductor containing one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound containing the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.

Next, a conductor 424 a and a conductor 424 b in contact with the conductor 405 a and the conductor 405 b, respectively, are formed (see FIG. 6A). The conductors 424 a and 424 b may be formed to have, for example, a single-layer structure or a stacked-layer structure including a conductor containing one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound containing the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.

Note that one conductor serving both as the conductors 405 a and 424 a may be used and one conductor serving both as the conductors 405 b and 424 b may be used.

In this manner, the transistor according to one embodiment of the present invention can be manufactured. The manufactured transistor does not necessarily include all the insulators, semiconductors, and conductors described above. For example, any one or more of the insulators 410 b and 418, the conductors 405 a, 405 b, 424 a, and 424 b, and the like may be omitted from the transistor in some cases.

FIG. 6B is a top view of the transistor. Each insulator and the conductors 405 a, 405 b, 424 a, and 424 b are omitted from the view for easy understanding.

As illustrated in FIG. 6B, the transistor does not have a region in which conductors overlap with each other with an insulator interposed therebetween. Therefore the transistor can be a transistor with low parasitic capacitance.

The transistor illustrated in FIGS. 6A and 6B has a surrounded channel (s-channel) structure, in which the semiconductor 406 is electrically surrounded by an electric field of the conductor 404. Therefore, a channel is formed in the entire semiconductor 406 (bulk) in some cases. In the s-channel structure, a large amount of current can flow between a source and a drain of a transistor, so that a high on-state current can be obtained.

The s-channel structure is suitable for a miniaturized transistor because a high on-state current can be obtained. A semiconductor device including the miniaturized transistor can have a high integration degree and high density. For example, the channel length of the transistor is preferably less than or equal to 40 nm, more preferably less than or equal to 30 nm, still more preferably less than or equal to 20 nm and the channel width of the transistor is preferably less than or equal to 40 nm, more preferably less than or equal to 30 nm, still more preferably less than or equal to 20 nm.

In the case where the transistor has the s-channel structure, a channel is formed in the whole of the semiconductor 406. Therefore, as the semiconductor 406 has a larger thickness, a channel region becomes larger. In other words, the thicker the semiconductor 406 is, the larger the on-state current of the transistor is. For example, the semiconductor 406 has a region with a thickness greater than or equal to 20 nm, preferably greater than or equal to 40 nm, more preferably greater than or equal to 60 nm, still more preferably greater than or equal to 100 nm. Note that the semiconductor 406 has a region with a thickness, for example, less than or equal to 300 nm, preferably less than or equal to 200 nm, more preferably less than or equal to 150 nm because the productivity of the semiconductor device might be decreased. Note that the transistor does not necessarily have the s-channel structure.

The structure in which the transistor includes one semiconductor layer is illustrated in FIG. 6A, but one embodiment of the present invention is not limited to this structure. The transistor may include a plurality of semiconductor layers. For example, as illustrated in FIG. 7A, the semiconductor 406 of the transistor may include a semiconductor 406 a, a semiconductor 406 b over the semiconductor 406 a, and a semiconductor 406 c over the semiconductor 406 b.

The semiconductor 406 b illustrated in FIG. 7A is an oxide semiconductor, for example. For the semiconductor 406 b, refer to the description of the semiconductor 406 illustrated in FIG. 2B and the like, for example.

For example, the semiconductors 406 a and 406 c contain one or more elements other than oxygen which are contained in the semiconductor 406 b. Since the semiconductors 406 a and 406 c each contain one or more elements other than oxygen which are contained in the semiconductor 406 b, an interface state is less likely to be formed at the interface between the semiconductors 406 a and 406 b and the interface between the semiconductors 406 b and 406 c.

The semiconductors 406 a, 406 b, and 406 c preferably contain at least indium. In the case of using an In-M-Zn oxide as the semiconductor 406 a, when the total atomic percentage of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be less than 50 atomic % and greater than or equal to 50 atomic %, respectively, more preferably less than 25 atomic % and greater than or equal to 75 atomic %, respectively. In the case of using an In-M-Zn oxide as the semiconductor 406 b, when the total atomic percentage of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be greater than or equal to 25 atomic % and less than 75 atomic %, respectively, more preferably greater than or equal to 34 atomic % and less than 66 atomic %, respectively. In the case of using an In-M-Zn oxide as the semiconductor 406 c, when the total atomic percentage of In and M is assumed to be 100 atomic %, the proportions of In and M are preferably set to be less than 50 atomic % and greater than or equal to 50 atomic %, respectively, more preferably less than 25 atomic % and greater than or equal to 75 atomic %, respectively. Note that the semiconductor 406 c may be formed using the same kind of oxide as that of the semiconductor 406 a.

As the semiconductor 406 b, an oxide having an electron affinity higher than those of the semiconductors 406 a and 406 c is used. For example, as the semiconductor 406 b, an oxide having an electron affinity higher than those of the semiconductors 406 a and 406 c by greater than or equal to 0.07 eV and less than or equal to 1.3 eV, preferably greater than or equal to 0.1 eV and less than or equal to 0.7 eV, further preferably greater than or equal to 0.15 eV and less than or equal to 0.4 eV is used. Note that the electron affinity refers to an energy difference between the vacuum level and the bottom of the conduction band.

An indium gallium oxide has a low electron affinity and a high oxygen-blocking property. Therefore, the semiconductor 406 c preferably includes an indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)] is, for example, greater than or equal to 70%, preferably greater than or equal to 80%, more preferably greater than or equal to 90%.

At this time, when a gate voltage is applied, a channel is formed in the semiconductor 406 b having the highest electron affinity among the semiconductors 406 a, 406 b, and 406 c.

Here, in some cases, there is a mixed region of the semiconductors 406 a and 406 b between the semiconductors 406 a and 406 b. Furthermore, in some cases, there is a mixed region of the semiconductors 406 b and 406 c between the semiconductors 406 b and 406 c. The mixed region has a low interface state density. For that reason, the stack including the semiconductors 406 a, 406 b, and 406 c has a band structure where energy at each interface and in the vicinity of the interface is changed continuously (continuous junction). Note that FIG. 32A is a cross-sectional view in which the semiconductors 406 a, 406 b, and 406 c are stacked in this order. FIG. 32B shows energy (Ec) at the bottom of the conduction band taken along the dashed-dotted line P1-P2 in FIG. 32A. FIG. 32B shows the case where the semiconductor 406 c has a higher electron affinity than the semiconductor 406 a. FIG. 32C shows the case where the semiconductor 406 c has a lower electron affinity than the semiconductor 406 a.

At this time, electrons move mainly in the semiconductor 406 b, not in the semiconductors 406 a and 406 c. When the interface state density at the interface between the semiconductors 406 a and 406 b and the interface state density at the interface between the semiconductors 406 b and 406 c are decreased, electron movement in the semiconductor 406 b is less likely to be inhibited and the on-sate current of the transistor can be increased.

Moreover, the thickness of the semiconductor 406 c is preferably as small as possible to increase the on-state current of the transistor. The thickness of the semiconductor 406 c is less than 10 nm, preferably less than or equal to 5 nm, more preferably less than or equal to 3 nm, for example. Meanwhile, the semiconductor 406 c has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) which are contained in an adjacent insulator into the semiconductor 406 b where a channel is formed. For this reason, it is preferable that the semiconductor 406 c have a certain thickness. The thickness of the semiconductor 406 c is greater than or equal to 0.3 nm, preferably greater than or equal to 1 nm, more preferably greater than or equal to 2 nm, for example. The semiconductor 406 c preferably has an oxygen blocking property to suppress outward diffusion of oxygen released from the insulator 402 and the like.

To improve reliability, preferably, the thickness of the semiconductor 406 a is large and the thickness of the semiconductor 406 c is small. For example, the semiconductor 406 a has a region with a thickness of, for example, greater than or equal to 10 nm, preferably greater than or equal to 20 nm, more preferably greater than or equal to 40 nm, still more preferably greater than or equal to 60 nm. An increase in the thickness of the semiconductor 406 a can increase the distance from an interface between the adjacent insulator and the semiconductor 406 a to the semiconductor 406 b in which a channel is formed. Since the productivity of the semiconductor device might be decreased, the semiconductor 406 a has a region with a thickness of, for example, less than or equal to 200 nm, preferably less than or equal to 120 nm, more preferably less than or equal to 80 nm.

For example, between the semiconductors 406 b and 406 a, a region in which the silicon concentration is less than 1×10¹⁹ atoms/cm³, preferably less than 5×10¹⁸ atoms/cm³, more preferably less than 2×10¹⁸ atoms/cm³ which is measured by SIMS is provided. Between the semiconductors 406 b and 406 c, a region in which the silicon concentration is less than 1×10¹⁹ atoms/cm³, preferably less than 5×10¹⁸ atoms/cm³, more preferably less than 2×10¹⁸ atoms/cm³ which is measured by SIMS is provided. The region in which the concentration of silicon is as above may be, for example, a region in which the conductor 404 and the semiconductor 406 overlap with each other.

It is preferable to reduce the concentration of hydrogen in the semiconductors 406 a and 406 c in order to reduce the concentration of hydrogen in the semiconductor 406 b. The semiconductors 406 a and 406 c each have a region in which the concentration of hydrogen measured by SIMS is less than or equal to 2×10²⁰ atoms/cm³, preferably less than or equal to 5×10¹⁹ atoms/cm³, more preferably less than or equal to 1×10¹⁹ atoms/cm³, still more preferably less than or equal to 5×10¹⁸ atoms/cm³. It is preferable to reduce the concentration of nitrogen in the semiconductors 406 a and 406 c in order to reduce the concentration of nitrogen in the semiconductor 406 b. The semiconductors 406 a and 406 c each have a region in which the nitrogen concentration measured by SIMS is lower than 5×10¹⁹ atoms/cm³, preferably less than or equal to 5×10¹⁸ atoms/cm³, more preferably less than or equal to 1×10¹⁸ atoms/cm³, still more preferably less than or equal to 5×10¹⁷ atoms/cm³.

In addition, the concentration of copper on the surface of or in the semiconductor 406 a is preferably as low as possible. For example, the semiconductor 406 a preferably has a region in which the copper concentration is less than or equal to 1×10¹⁹ atoms/cm³, less than or equal to 5×10¹⁸ atoms/cm³, or less than or equal to 1×10¹⁸ atoms/cm³. Furthermore, the concentration of copper on the surface of or in the semiconductor 406 c is preferably as low as possible. For example, the semiconductor 406 c preferably has a region in which the copper concentration is less than or equal to 1×10¹⁹ atoms/cm³, less than or equal to 5×10¹⁸ atoms/cm³, or less than or equal to 1×10¹⁸ atoms/cm³.

The above three-layer structure is an example. For example, the semiconductor 406 may have a two-layer structure without the semiconductor 406 a or the semiconductor 406 c. The semiconductor 406 may have a four-layer structure in which any one of the semiconductors described as examples of the semiconductors 406 a, 406 b, and 406 c is provided below or over the semiconductor 406 a or below or over the semiconductor 406 c. The semiconductor 406 may have a n-layer structure (n is an integer of 5 or more) in which any one of the semiconductors described as examples of the semiconductors 406 a, 406 b, and 406 c is provided at two or more of the following positions: over the semiconductor 406 a, below the semiconductor 406 a, over the semiconductor 406 c, and below the semiconductor 406 c.

As illustrated in FIG. 7B, the semiconductor 406 of the transistor may include the semiconductors 406 a and 406 b over the semiconductor 406 a, for example. In addition, the insulator 412 may include the insulators 412 a and 412 b over the insulator 412 a.

For the insulator 412 b, refer to the description of the insulator 412 illustrated in FIG. 3B and the like, for example. For the insulator 412 a, refer to the description of the semiconductor 406 c illustrated in FIG. 7A and the like, for example. In other words, the insulator 412 a may be a semiconductor.

A structure similar to that in FIG. 7A is illustrated in FIG. 7B, in which the semiconductor 406 b including the channel formation region of the transistor is interposed between the semiconductor 406 a and the insulator 412 a. Hence, the transistor illustrated in FIG. 7B is a transistor having high on-state current. In addition, in the transistor illustrated in FIG. 7B, the semiconductor 406 b is surrounded by the semiconductor 406 a and the insulator 412 a along the channel width direction. Hence, the interface state density is also reduced at a side surface of the semiconductor 406 b.

Furthermore, a conductor 413 may be present below the transistor as illustrated in FIG. 8A, for example. The conductor 413 has, for example, a function of shielding the transistor from light. When the conductor 413 is used to shield the transistor from light, the conductor 413 is preferably larger than the semiconductor 406 in some cases, for example. Alternatively, the conductor 413 serves, for example, as a second gate electrode of the transistor. When the conductor 413 is used as a second gate electrode of the transistor, the threshold voltage of the transistor can be controlled with a potential applied to the conductor 413, for example.

For example, by applying a lower voltage or a higher voltage than a source electrode to the conductor 413, the threshold voltage of the transistor may be shifted in the positive direction or the negative direction. By shifting the threshold voltage of the transistor in the positive direction, a normally-off transistor in which the transistor is in a non-conduction state (off state) even when the gate voltage is 0 V can be achieved in some cases. The voltage applied to the conductor 413 may be a variable or a fixed voltage. When the voltage applied to the conductor 413 is a variable, a circuit controlling the voltage may be electrically connected to the conductor 413.

The conductor 413 may be formed to have, for example, a single-layer structure or a stacked-layer structure including a conductor containing one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound containing the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.

The transistor may have a structure in which, for example, the conductors 404 and 413 are electrically connected to each other through a conductor 415 as illustrated in FIG. 8B. With such a structure, the conductors 404 and 413 are supplied with the same potential; consequently, switching characteristics of the transistor can be improved.

The conductor 415 may be formed to have, for example, a single-layer structure or a stacked-layer structure including a conductor containing one or more kinds of boron, nitrogen, oxygen, fluorine, silicon, phosphorus, aluminum, titanium, chromium, manganese, cobalt, nickel, copper, zinc, gallium, yttrium, zirconium, molybdenum, ruthenium, silver, indium, tin, tantalum, and tungsten. An alloy or a compound containing the above element may be used, for example, and a conductor containing aluminum, a conductor containing copper and titanium, a conductor containing copper and manganese, a conductor containing indium, tin, and oxygen, a conductor containing titanium and nitrogen, or the like may be used.

As illustrated in FIG. 33A, the conductor 413 may be wider than (protrude laterally from) the conductor 404 along the channel length direction. This shape can improve the light-blocking function. Alternatively, as illustrated in FIG. 33B, the conductor 413 may be narrower (on the inner side) than the conductor 404 along the channel length direction. This shape can reduce parasitic capacitance. Note that the conductor 415 may be omitted as in FIG. 33A or may be provided as illustrated in FIG. 33B.

<Transistor Structure 2>

Next, a transistor and a method of manufacturing the transistor having a structure different from that of the above-described transistor are described. Note that the method of manufacturing the transistor is described using cross sections along the channel length direction (B1-B2 cross section) and the channel width direction (B3-B4 cross section).

First, the substrate 500 is prepared.

For the substrate 500, refer to the description of the substrate 400, for example.

Next, an insulator 502 is formed. For the insulator 502, refer to the description of the insulator 402, for example.

Next, a semiconductor 506 is formed. The semiconductor 506 is formed in such a manner that the conductor to be the semiconductor 506 is formed and then partly etched.

For the semiconductor 506, refer to the description of the semiconductor 406, for example.

Next, an insulator 542 and a conductor 534 are formed in this order (see FIG. 9A). For the insulator 542, refer to the description of the insulator 442, for example. For the conductor 534, refer to the description of the conductor 434, for example.

Next, the conductor 534 is partly etched, so that a conductor 504 is formed (see FIG. 9B).

Next, an insulator 508 is formed (see FIG. 10A). The insulator 508 may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. The insulator 508 may include an insulator containing nitrogen such as silicon nitride oxide or silicon nitride.

Next, treatment for adding an impurity 550 is performed (see FIG. 10B). For the treatment of adding the impurity 550, refer to the description of the treatment of adding the impurity 450.

The impurity 550 is added to a region in the vicinity of surfaces of the insulator 502 and the semiconductor 506, and the like. The region is referred to as a region 554 (see FIG. 11A). For the region 554, refer to the description of the region 454.

Next, an insulator 520 is formed (see FIG. 11B). Then, the insulators 520 and 508 are anisotropically etched, so that an insulator 510 in contact with a side surface of the conductor 504 is formed. For the insulator 510, refer to the description of the insulator 410 a, for example. Note that the insulator 542 is etched during the anisotropic etching, thereby forming an insulator 512. At the same time, the insulator 502 is half-etched, and thus part of the insulator 502 is removed (see FIG. 12A).

Next, a conductor is selectively grown over an exposed region of the region 554. Consequently, a conductor 516 a and a conductor 516 b are formed over the semiconductor 506. In addition, a conductor 516 c is formed over the conductor 504 (see FIG. 12B). For selective growth of the conductors 516 a, 516 b, and 516 c, refer to the description of the selective growth of the conductor 106.

Next, an insulator 518 is formed. For the insulator 518, refer to the description of the insulator 418, for example.

Next, an opening reaching the conductor 516 a and an opening reaching the conductor 516 b are formed in the insulator 518, and conductors 505 a and 505 b are embedded in their respective openings. Note that the openings may penetrate the conductors 516 a and 516 b to reach the semiconductor 506. For the conductors 505 a and 505 b, refer to the description of the conductors 405 a and 405 b, for example.

Next, a conductor 524 a and a conductor 524 b in contact with the conductor 505 a and the conductor 505 b, respectively, are formed (see FIG. 13A). For the conductors 524 a and 524 b, refer to the description of the conductors 424 a and 424 b, for example.

In this manner, the transistor according to one embodiment of the present invention can be manufactured. The manufactured transistor does not necessarily include all the insulators, semiconductors, and conductors described above. For example, any one or more of the insulator 518, the conductors 505 a, 505 b, 524 a, and 524 b, and the like may be omitted from the transistor in some cases.

FIG. 13B is a top view of the transistor. Each insulator and the conductors 505 a, 505 b, 524 a, and 524 b are omitted from the view for easy understanding.

As illustrated in FIG. 13B, the transistor does not have a region in which conductors overlap with each other with an insulator interposed therebetween. Therefore the transistor can be a transistor with low parasitic capacitance.

The transistor illustrated in FIGS. 13A and 13B has an s-channel structure in which the semiconductor 506 is electrically surrounded by an electric field of the conductor 504. Therefore, a large amount of current can flow between a source and a drain of a transistor, so that a high on-state current can be obtained. Note that the transistor does not necessarily have an s-channel structure.

The structure in which the transistor includes one semiconductor layer is illustrated in FIG. 13A, but one embodiment of the present invention is not limited to this structure. The transistor may include a plurality of semiconductor layers. For example, as illustrated in FIG. 14A, the semiconductor 506 of the transistor may include a semiconductor 506 a, a semiconductor 506 b over the semiconductor 506 a, and a semiconductor 506 c over the semiconductor 506 b.

For the semiconductor 506 b illustrated in FIG. 14A, refer to the description of the semiconductor 406 b, for example. For the semiconductor 506 a, refer to the description of the semiconductor 406 a, for example. For the semiconductor 506 c, refer to the description of the semiconductor 406 c, for example.

As illustrated in FIG. 14B, the semiconductor 506 of the transistor may include the semiconductor 506 a and the semiconductor 506 b over the semiconductor 506 a, for example. In addition, the insulator 512 may include the insulator 512 a and the insulator 512 b over the insulator 512 a.

For the insulator 512 b, refer to the description of the insulator 412 b, for example. For the insulator 512 a, refer to the description of the insulator 412 a, for example.

A structure similar to that in FIG. 14A is illustrated in FIG. 14B, in which the semiconductor 506 b including the channel formation region of the transistor is interposed between the semiconductor 506 a and the insulator 512 a. Hence, the transistor illustrated in FIG. 14B is a transistor having high on-state current. In addition, in the transistor illustrated in FIG. 14B, the semiconductor 506 b is surrounded by the semiconductor 506 a and the insulator 512 a along the channel width direction. Hence, the interface state density is also reduced at a side surface of the semiconductor 506 b.

Furthermore, a conductor 513 may be present below the transistor as illustrated in FIG. 15A, for example. For the conductor 513, refer to the description of the conductor 413, for example.

The transistor may have a structure in which, for example, the conductors 504 and 513 are electrically connected to each other through a conductor 515 as illustrated in FIG. 15B. With such a structure, the conductors 504 and 513 are supplied with the same potential; consequently, switching characteristics of the transistor can be improved. For the conductor 515, refer to the description of the conductor 415, for example.

As illustrated in FIG. 34A, the conductor 513 may be wider than (protrude laterally from) the conductor 504 along the channel length direction. This shape can improve the light-blocking function. Alternatively, as illustrated in FIG. 34B, the conductor 513 may be narrower (on the inner side) than the conductor 504 along the channel length direction. This shape can reduce parasitic capacitance. Note that the conductor 515 may be omitted as in FIG. 34A or may be provided as illustrated in FIG. 34B.

The transistor structures described above are merely examples, and a transistor structure obtained by combining any of them is also included in the category of one embodiment of the present invention.

<Semiconductor Device>

An example of a semiconductor device according to one embodiment of the present invention is described below.

An example of a semiconductor device including a transistor according to one embodiment of the present invention is described below.

FIG. 16A is a cross-sectional view of a semiconductor device according to one embodiment of the present invention. The semiconductor device illustrated in FIG. 16A includes a transistor 2200 using a first semiconductor in a lower portion and a transistor 2100 using a second semiconductor in an upper portion. FIG. 16A shows an example in which the transistor illustrated in FIGS. 6A and 6B is used as the transistor 2100 using the second semiconductor.

As the first semiconductor, a semiconductor having an energy gap different from that of the second semiconductor may be used. For example, the first semiconductor is a semiconductor other than an oxide semiconductor and the second semiconductor is an oxide semiconductor. As the first semiconductor, silicon, germanium, or the like which has a polycrystalline structure, a single crystal structure, or the like may be used. Alternatively, a semiconductor having distortion such as distorted silicon may be used. Alternatively, as the first semiconductor, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like which can be used for a high-electron-mobility (HEMT) may be used. By using any of these semiconductors as the first semiconductor, the transistor 2200 capable of high speed operation can be obtained. By using an oxide semiconductor as the second semiconductor, the transistor 2100 with a low off-state current can be obtained.

Note that the transistor 2200 may be either an n-channel transistor or a p-channel transistor, and an appropriate transistor is used in accordance with a circuit. As the transistor 2100 and/or the transistor 2200, the above-described transistor or the transistor illustrated in FIG. 16A is not necessarily used in some cases.

The semiconductor device illustrated in FIG. 16A includes the transistor 2100 above the transistor 2200 with insulators 2201 and 2207 provided therebetween. Between the transistors 2200 and 2100, a plurality of conductors 2202 which function as wirings are provided. Wirings or electrodes provided in an upper layer and a lower layer are electrically connected to each other by a plurality of conductors 2203 embedded in insulating films. Furthermore, the semiconductor device includes an insulator 2204 over the transistor 2100 and a conductor 2205 over the insulator 2204.

The insulator 2204 may be formed to have, for example, a single-layer structure or a stacked-layer structure including an insulator containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, or tantalum. Note that the insulator 2204 may include an insulator containing nitrogen such as silicon nitride oxide or silicon nitride.

A resin may be used as the insulator 2204. For example, a resin containing polyimide, polyamide, acrylic, silicone, or the like may be used. The use of a resin does not need planarization treatment performed on the top surface of the insulator 2204 in some cases. By using a resin, a thick film can be formed in a short time; thus, the productivity can be increased.

By stacking a plurality of transistors, a plurality of circuits can be arranged with high density.

Here, in the case where single crystal silicon included in a semiconductor substrate 2211 is used as the first semiconductor of the transistor 2200, the hydrogen concentration in an insulator near the first semiconductor of the transistor 2200 is preferably high. The hydrogen terminates dangling bonds of silicon, so that the reliability of the transistor 2200 can be increased. On the other hand, in the case where an oxide semiconductor is used as the second semiconductor of the transistor 2100, the hydrogen concentration in an insulator near the second semiconductor of the transistor 2100 is preferably low. The hydrogen causes generation of carriers in the oxide semiconductor, which might lead to a decrease in the reliability of the transistor 2100. Therefore, in the case where the transistor 2200 using single crystal silicon and the transistor 2100 using an oxide semiconductor are stacked, providing the insulator 2207 having a function of blocking hydrogen between the transistors is effective in increasing the reliability of the transistors.

The insulator 2207 may be, for example, formed to have a single-layer structure or a stacked-layer structure using an insulator containing aluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride, yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, yttria-stabilized zirconia (YSZ), or the like.

Furthermore, an insulator having a function of blocking hydrogen is preferably formed over the transistor 2100 to cover the transistor 2100 using an oxide semiconductor. As the insulator, an insulator that is similar to the insulator 2207 can be used, and in particular, an aluminum oxide film is preferably used. The aluminum oxide film has a high blocking effect of preventing penetration of both oxygen and impurities such as hydrogen and moisture. Thus, by using the aluminum oxide film as an insulator covering the transistor 2100, release of oxygen from the oxide semiconductor included in the transistor 2100 can be prevented and entry of water and hydrogen into the oxide semiconductor can be prevented.

Note that the transistor 2200 can be a transistor of various types without being limited to a planar type transistor. For example, a FIN-type transistor can be used. An example of a cross-sectional view in this case is shown in FIG. 16B. An insulator 2212 is placed over a semiconductor substrate 2211. The semiconductor substrate 2211 includes a projection with a thin tip (also referred to a fin). Alternatively, the projection does not necessarily have the thin tip; a projection with a cuboid-like projection and a projection with a thick tip are permitted, for example. A gate insulator 2214 is placed over the projection of the semiconductor substrate 2211, and a gate electrode 2213 is placed over the gate insulator 2214. Source and drain regions 2215 are formed in the semiconductor substrate 2211. Note that here is shown an example in which the semiconductor substrate 2211 includes the projection; however, a semiconductor device according to one embodiment of the present invention is not limited thereto. For example, a semiconductor region having a projection may be formed by processing an SOI substrate.

In the above circuit, electrodes of the transistors 2100 and 2200 can be connected in a variety of ways; thus, a variety of circuits can be formed. Examples of circuit configurations which can be achieved by using a semiconductor device according to one embodiment of the present invention are described below.

A circuit diagram in FIG. 17A shows a configuration of a so-called CMOS inverter in which the p-channel transistor 2200 and the n-channel transistor 2100 are connected to each other in series and in which gates of them are connected to each other.

A circuit diagram in FIG. 17B shows a configuration in which sources of the transistors 2100 and 2200 are connected to each other and drains of the transistors 2100 and 2200 are connected to each other. With such a configuration, the transistors can function as a so-called CMOS analog switch.

An example of a semiconductor device (memory device) including the transistor according to one embodiment of the present invention, which can retain stored data even when not powered, and which has an unlimited number of write cycles is illustrated in FIGS. 18A and 18B.

The semiconductor device illustrated in FIG. 18A includes a transistor 3200 using a first semiconductor, a transistor 3300 using a second semiconductor, and a capacitor 3400. Note that the above-described transistor can be used as the transistor 3300.

The transistor 3300 is a transistor using an oxide semiconductor. Since the off-state current of the transistor 3300 is low, stored data can be retained for a long period at a predetermined node of the semiconductor device. In other words, power consumption of the semiconductor device can be reduced because refresh operation becomes unnecessary or the frequency of refresh operation can be extremely low.

In FIG. 18A, a first wiring 3001 is electrically connected to a source of the transistor 3200. A second wiring 3002 is electrically connected to a drain of the transistor 3200. A third wiring 3003 is electrically connected to one of the source and the drain of the transistor 3300. A fourth wiring 3004 is electrically connected to the gate of the transistor 3300. The gate of the transistor 3200 and the other of the source and the drain of the transistor 3300 are electrically connected to the one electrode of the capacitor 3400. A fifth wiring 3005 is electrically connected to the other electrode of the capacitor 3400.

The semiconductor device in FIG. 18A is capable of retaining the potential of the gate of the transistor 3200, and thus enables writing, retaining, and reading of data as follows.

Writing and retaining of data are described. First, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned on, so that the transistor 3300 is turned on. Accordingly, the potential of the third wiring 3003 is supplied to a node FG where the gate of the transistor 3200 and the one electrode of the capacitor 3400 are electrically connected to each other. That is, a predetermined charge is supplied to the gate of the transistor 3200 (writing). Here, one of two kinds of charges providing different potential levels (hereinafter referred to as a low-level charge and a high-level charge) is supplied. After that, the potential of the fourth wiring 3004 is set to a potential at which the transistor 3300 is turned off, so that the transistor 3300 is turned off. Thus, the charge is held at the node FG (retaining).

Since the off-state current of the transistor 3300 is extremely low, the charge of the node FG is retained for a long time.

Next, reading of data is described. An appropriate potential (a reading potential) is supplied to the fifth wiring 3005 while a predetermined potential (a constant potential) is supplied to the first wiring 3001, whereby the potential of the second wiring 3002 varies depending on the amount of charge retained in the node FG. This is because in the case of using an n-channel transistor as the transistor 3200, an apparent threshold voltage V_(th) _(—) _(H) at the time when the high-level charge is given to the gate of the transistor 3200 is lower than an apparent threshold voltage V_(th) _(—) _(L) at the time when the low-level charge is given to the gate of the transistor 3200. Here, an apparent threshold voltage refers to the potential of the fifth wiring 3005 which is needed to turn on the transistor 3200. Thus, the potential of the fifth wiring 3005 is set to a potential V₀ which is between V_(th) _(—) _(H) and V_(th) _(—) _(L), whereby charge supplied to the node FG can be determined. For example, in the case where the high-level charge is supplied to the node FG in writing and the potential of the fifth wiring 3005 is V₀ (>V_(th) _(—) _(H)), the transistor 3200 is turned on. On the other hand, in the case where the low-level charge is supplied to the node FG in writing, even when the potential of the fifth wiring 3005 is V₀ (<V_(th) _(—) _(L)), the transistor 3200 remains off. Thus, the data retained in the node FG can be read by determining the potential of the second wiring 3002.

Note that in the case where memory cells are arrayed, it is necessary that data of a desired memory cell be read in read operation. In the case where data of the other memory cells is not read, the fifth wiring 3005 is preferably supplied with a potential at which the transistor 3200 is turned off regardless of the charge supplied to the node FG, that is, a potential lower than V_(th) _(—) _(H). Alternatively, the fifth wiring 3005 is preferably supplied with a potential at which the transistor 3200 is turned on regardless of the charge supplied to the node FG, that is, a potential higher than V_(th) _(—) _(L).

The semiconductor device in FIG. 18B is different form the semiconductor device in FIG. 18A in that the transistor 3200 is not provided. Also in this case, writing and retaining operation of data can be performed in a manner similar to that of the semiconductor device illustrated in FIG. 18A.

Reading of data in the semiconductor device in FIG. 18B is described. When the transistor 3300 is turned on, the third wiring 3003 which is in a floating state and the capacitor 3400 are electrically connected to each other, and the charge is redistributed between the third wiring 3003 and the capacitor 3400. As a result, the potential of the third wiring 3003 is changed. The amount of change in the potential of the third wiring 3003 varies depending on the potential of the one electrode of the capacitor 3400 (or the charge accumulated in the capacitor 3400).

For example, the potential of the third wiring 3003 after the charge redistribution is (C_(B)×V_(B0)+C×V)/(C_(B)+C), where V is the potential of the one electrode of the capacitor 3400, C is the capacitance of the capacitor 3400, C_(B) is the capacitance component of the third wiring 3003, and V_(B0) is the potential of the third wiring 3003 before the charge redistribution. Thus, it can be found that, assuming that the memory cell is in either of two states in which the potential of the one electrode of the capacitor 3400 is V₁ and V₀ (V₁>V₀), the potential of the third wiring 3003 in the case of retaining the potential V₁ (=(C_(B)×V_(B0)+C×V₁)/(C_(B)+C)) is higher than the potential of the third wiring 3003 in the case of retaining the potential V₀ (=(C_(B)×V_(B0)+C×V₀)/(C_(B)+C)).

Then, by comparing the potential of the third wiring 3003 with a predetermined potential, data can be read.

In this case, a transistor including the first semiconductor may be used for a driver circuit for driving a memory cell, and a transistor including the second semiconductor may be stacked over the driver circuit as the transistor 3300.

When including a transistor using an oxide semiconductor and having an extremely low off-state current, the semiconductor device described above can retain stored data for a long time. In other words, refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely low, which leads to a sufficient reduction in power consumption. Moreover, stored data can be retained for a long time even when power is not supplied (note that a potential is preferably fixed).

In the semiconductor device, high voltage is not needed for writing data and elements are less likely to deteriorate. Unlike in a conventional nonvolatile memory, for example, it is not necessary to inject and extract electrons into and from a floating gate; thus, a problem such as deterioration of an insulator is not caused. That is, the semiconductor device according to one embodiment of the present invention does not have a limit on the number of times data can be rewritten, which is a problem of a conventional nonvolatile memory, and the reliability thereof is drastically improved. Furthermore, because data is written depending on the state of the transistor (on or off), high-speed operation can be easily achieved.

<RF Tag>

An RF tag including the above-described transistor or the above-described memory device is described below with reference to FIG. 19.

The RF tag according to one embodiment of the present invention includes a memory circuit, stores data in the memory circuit, and transmits and receives data to/from the outside by using contactless means, for example, wireless communication. With these features, the RF tag can be used for an individual authentication system in which an object or the like is recognized by reading the individual information, for example. Note that the RF tag is required to have high reliability in order to be used for this purpose.

A configuration of the RF tag is described with reference to FIG. 19. FIG. 19 is a block diagram illustrating a configuration example of the RF tag.

As shown in FIG. 19, an RF tag 800 includes an antenna 804 which receives a radio signal 803 transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator, a reader/writer, or the like). The RF tag 800 includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. A semiconductor of a transistor having a rectifying function included in the demodulation circuit 807 may be a material which enables a reverse current to be low enough, for example, an oxide semiconductor. This can suppress the phenomenon of a rectifying function becoming weaker due to generation of a reverse current and prevent saturation of the output from the demodulation circuit. In other words, the input to the demodulation circuit and the output from the demodulation circuit can have a relation closer to a linear relation. Note that data transmission methods are roughly classified into the following three methods: an electromagnetic coupling method in which a pair of coils is provided so as to face each other and communicates with each other by mutual induction, an electromagnetic induction method in which communication is performed using an induction field, and a radio wave method in which communication is performed using a radio wave. Any of these methods can be used in the RF tag 800.

Next, the configuration of each circuit is described. The antenna 804 exchanges the radio signal 803 with the antenna 802 connected to the communication device 801. The rectifier circuit 805 generates an input potential by rectification, for example, half-wave voltage doubler rectification of an input alternating signal generated by reception of a radio signal at the antenna 804 and smoothing of the rectified signal with a capacitor provided in a later stage in the rectifier circuit 805. Note that a limiter circuit may be provided on an input side or an output side of the rectifier circuit 805. The limiter circuit controls electric power so that electric power which is higher than or equal to certain electric power is not input to a circuit in a later stage if the amplitude of the input alternating signal is high and an internal generation voltage is high.

The constant voltage circuit 806 generates a stable power supply voltage from an input potential and supplies it to each circuit. Note that the constant voltage circuit 806 may include a reset signal generation circuit. The reset signal generation circuit is a circuit which generates a reset signal of the logic circuit 809 by utilizing rise of the stable power supply voltage.

The demodulation circuit 807 demodulates the input alternating signal by envelope detection and generates the demodulated signal. Furthermore, the modulation circuit 808 performs modulation in accordance with data to be output from the antenna 804.

The logic circuit 809 analyzes and processes the demodulated signal. The memory circuit 810 holds the input data and includes a row decoder, a column decoder, a memory region, and the like. Furthermore, the ROM 811 stores an identification number (ID) or the like and outputs it in accordance with processing.

Note that the decision whether each circuit described above is provided or not can be made as appropriate.

Here, the above-described memory device can be used as the memory circuit 810. Since the memory device according to one embodiment of the present invention can retain data even when not powered, the memory device is suitable for an RF tag. Furthermore, the memory device according to one embodiment of the present invention needs power (voltage) needed for data writing lower than that needed in a conventional nonvolatile memory; thus, it is possible to prevent a difference between the maximum communication range in data reading and that in data writing. In addition, it is possible to suppress malfunction or incorrect writing which is caused by power shortage in data writing.

Since the memory device according to one embodiment of the present invention can be used as a nonvolatile memory, it can also be used as the ROM 811. In this case, it is preferable that a manufacturer separately prepare a command for writing data to the ROM 811 so that a user cannot rewrite data freely. Since the manufacturer gives identification numbers before shipment and then starts shipment of products, instead of putting identification numbers to all the manufactured RF tags, it is possible to put identification numbers to only good products to be shipped. Thus, the identification numbers of the shipped products are in series and customer management corresponding to the shipped products is easily performed.

<Application Examples of RF Tag>

Application examples of the RF tag according to one embodiment of the present invention are described below with reference to FIGS. 20A to 20F. The RF tag is widely used and can be provided for, for example, products such as bills, coins, securities, bearer bonds, documents (e.g., driver's licenses or resident's cards, see FIG. 20A), packaging containers (e.g., wrapping paper or bottles, see FIG. 20C), recording media (e.g., DVDs or video tapes, see FIG. 20B), vehicles (e.g., bicycles, see FIG. 20D), personal belongings (e.g., bags or glasses), foods, plants, animals, human bodies, clothing, household goods, medical supplies such as medicine and chemicals, and electronic devices (e.g., liquid crystal display devices, EL display devices, television sets, or cellular phones), or tags on products (see FIGS. 20E and 20F).

An RF tag 4000 according to one embodiment of the present invention is fixed on products by, for example, being attached to a surface thereof or being embedded therein. For example, the RF tag 4000 is fixed to each product by being embedded in paper of a book, or embedded in an organic resin of a package. The RF tag 4000 according to one embodiment of the present invention is small, thin, and lightweight, so that the design of a product is not impaired even after the RF tag 4000 is fixed thereto. Furthermore, bills, coins, securities, bearer bonds, documents, or the like can have identification functions by being provided with the RF tag 4000 according to one embodiment of the present invention, and the identification functions can be utilized to prevent counterfeits. Moreover, the efficiency of a system such as an inspection system can be improved by providing the RF tag 4000 according to one embodiment of the present invention for packaging containers, recording media, personal belongings, foods, clothing, household goods, electronic devices, or the like. Vehicles can also have higher security against theft or the like by being provided with the RF tag 4000 according to one embodiment of the present invention.

As described above, the RF tag according to one embodiment of the present invention can be used for the above-described purposes.

<CPU>

A CPU including a semiconductor device such as the above-described transistor or the above-described memory device is described below.

FIG. 21 is a block diagram illustrating a configuration example of a CPU including the above-described transistor as a component.

The CPU illustrated in FIG. 21 includes, over a substrate 1190, an arithmetic logic unit (ALU) 1191, an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, a bus interface (Bus I/F) 1198, a rewritable ROM 1199, and a ROM interface (ROM I/F) 1189. A semiconductor substrate, an SOI substrate, a glass substrate, or the like is used as the substrate 1190. The ROM 1199 and the ROM interface (ROM I/F) 1189 may be provided over a separate chip. Needless to say, the CPU in FIG. 21 is just an example in which the configuration is simplified, and an actual CPU may have a variety of configurations depending on the application. For example, the CPU may have the following configuration: a structure including the CPU illustrated in FIG. 21 or an arithmetic circuit is considered as one core; a plurality of the cores are included; and the cores operate in parallel. The number of bits that the CPU can process in an internal arithmetic circuit or in a data bus can be 8, 16, 32, or 64, for example.

An instruction that is input to the CPU through the bus interface 1198 is input to the instruction decoder 1193 and decoded therein, and then, input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 conduct various controls in accordance with the decoded instruction. Specifically, the ALU controller 1192 generates signals for controlling the operation of the ALU 1191. While the CPU is executing a program, the interrupt controller 1194 judges an interrupt request from an external input/output device or a peripheral circuit on the basis of its priority or a mask state, and processes the request. The register controller 1197 generates an address of the register 1196, and reads/writes data from/to the register 1196 in accordance with the state of the CPU.

The timing controller 1195 generates signals for controlling operation timings of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generator for generating an internal clock signal CLK2 based on a reference clock signal CLK1, and supplies the internal clock signal CLK2 to the above circuits.

In the CPU illustrated in FIG. 21, a memory cell is provided in the register 1196. For the memory cell of the register 1196, the above-described transistor, the above-described memory device, or the like can be used.

In the CPU illustrated in FIG. 21, the register controller 1197 selects operation of retaining data in the register 1196 in accordance with an instruction from the ALU 1191. That is, the register controller 1197 selects whether data is retained by a flip-flop or by a capacitor in the memory cell included in the register 1196. When data retaining by the flip-flop is selected, a power supply voltage is supplied to the memory cell in the register 1196. When data retaining by the capacitor is selected, the data is rewritten in the capacitor, and supply of power supply voltage to the memory cell in the register 1196 can be stopped.

FIG. 22 is an example of a circuit diagram of a memory element 1200, which can be used as the register 1196. The memory element 1200 includes a circuit 1201 in which stored data is volatile when power supply is stopped, a circuit 1202 in which stored data is nonvolatile even when power supply is stopped, a switch 1203, a switch 1204, a logic element 1206, a capacitor 1207, and a circuit 1220 having a selecting function. The circuit 1202 includes a capacitor 1208, a transistor 1209, and a transistor 1210. Note that the memory element 1200 may further include another element such as a diode, a resistor, or an inductor, as needed.

Here, the above-described memory device can be used as the circuit 1202. When supply of a power supply voltage to the memory element 1200 is stopped, GND (0 V) or a potential at which the transistor 1209 in the circuit 1202 is turned off continues to be input to a gate of the transistor 1209. For example, the gate of the transistor 1209 is grounded through a load such as a resistor.

Shown here is an example in which the switch 1203 is a transistor 1213 having one conductivity type (e.g., an n-channel transistor) and the switch 1204 is a transistor 1214 having a conductivity type opposite to the one conductivity type (e.g., a p-channel transistor). A first terminal of the switch 1203 corresponds to one of a source and a drain of the transistor 1213, a second terminal of the switch 1203 corresponds to the other of the source and the drain of the transistor 1213, and conduction or non-conduction between the first terminal and the second terminal of the switch 1203 (i.e., the on/off state of the transistor 1213) is selected by a control signal RD input to a gate of the transistor 1213. A first terminal of the switch 1204 corresponds to one of a source and a drain of the transistor 1214, a second terminal of the switch 1204 corresponds to the other of the source and the drain of the transistor 1214, and conduction or non-conduction between the first terminal and the second terminal of the switch 1204 (i.e., the on/off state of the transistor 1214) is selected by the control signal RD input to a gate of the transistor 1214.

One of a source and a drain of the transistor 1209 is electrically connected to one of a pair of electrodes of the capacitor 1208 and a gate of the transistor 1210. Here, the connection portion is referred to as a node M2. One of a source and a drain of the transistor 1210 is electrically connected to a wiring which can supply a low power supply potential (e.g., a GND line), and the other thereof is electrically connected to the first terminal of the switch 1203 (the one of the source and the drain of the transistor 1213). The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is electrically connected to the first terminal of the switch 1204 (the one of the source and the drain of the transistor 1214). The second terminal of the switch 1204 (the other of the source and the drain of the transistor 1214) is electrically connected to a wiring which can supply a power supply potential VDD. The second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213), the first terminal of the switch 1204 (the one of the source and the drain of the transistor 1214), an input terminal of the logic element 1206, and one of a pair of electrodes of the capacitor 1207 are electrically connected to each other. Here, the connection portion is referred to as a node M1. The other of the pair of electrodes of the capacitor 1207 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 1207 can be supplied with a low power supply potential (e.g., GND) or a high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 1207 is electrically connected to the wiring which can supply a low power supply potential (e.g., a GND line). The other of the pair of electrodes of the capacitor 1208 can be supplied with a constant potential. For example, the other of the pair of electrodes of the capacitor 1208 can be supplied with the low power supply potential (e.g., GND) or the high power supply potential (e.g., VDD). The other of the pair of electrodes of the capacitor 1208 is electrically connected to the wiring which can supply a low power supply potential (e.g., a GND line).

The capacitor 1207 and the capacitor 1208 are not necessarily provided as long as the parasitic capacitance of the transistor, the wiring, or the like is actively utilized.

A control signal WE is input to the gate of the transistor 1209. As for each of the switch 1203 and the switch 1204, a conduction state or a non-conduction state between the first terminal and the second terminal is selected by the control signal RD which is different from the control signal WE. When the first terminal and the second terminal of one of the switches are in the conduction state, the first terminal and the second terminal of the other of the switches are in the non-conduction state.

A signal corresponding to data retained in the circuit 1201 is input to the other of the source and the drain of the transistor 1209. FIG. 22 illustrates an example in which a signal output from the circuit 1201 is input to the other of the source and the drain of the transistor 1209. The logic value of a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is inverted by the logic element 1206, and the inverted signal is input to the circuit 1201 through the circuit 1220.

In the example of FIG. 22, a signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) is input to the circuit 1201 through the logic element 1206 and the circuit 1220; however, one embodiment of the present invention is not limited thereto. The signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) may be input to the circuit 1201 without its logic value being inverted. For example, in the case where the circuit 1201 includes a node in which a signal obtained by inversion of the logic value of a signal input from the input terminal is retained, the signal output from the second terminal of the switch 1203 (the other of the source and the drain of the transistor 1213) can be input to the node.

In FIG. 22, the transistors included in the memory element 1200 except for the transistor 1209 can each be a transistor in which a channel is formed in a film formed using a semiconductor other than an oxide semiconductor or in the substrate 1190. For example, the transistor can be a transistor whose channel is formed in a film formed using silicon or a silicon substrate. Alternatively, all the transistors in the memory element 1200 may be transistors in which a channel is formed in an oxide semiconductor. Further alternatively, in the memory element 1200, a transistor in which a channel is formed in an oxide semiconductor can be included besides the transistor 1209, and a transistor in which a channel is formed in a layer or the substrate 1190 including a semiconductor other than an oxide semiconductor can be used for the rest of the transistors.

As the circuit 1201 in FIG. 22, for example, a flip-flop circuit can be used. As the logic element 1206, for example, an inverter, a clocked inverter, or the like can be used.

In a period during which the memory element 1200 is not supplied with the power supply voltage, the semiconductor device according to one embodiment of the present invention can retain data stored in the circuit 1201 by the capacitor 1208 which is provided in the circuit 1202.

The off-state current of a transistor in which a channel is formed in an oxide semiconductor is extremely low. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor is significantly lower than that of a transistor in which a channel is formed in silicon having crystallinity. Thus, when the transistor is used as the transistor 1209, a signal held in the capacitor 1208 is retained for a long time also in a period during which the power supply voltage is not supplied to the memory element 1200. The memory element 1200 can accordingly retain the stored content (data) also in a period during which the supply of the power supply voltage is stopped.

Since the memory element performs pre-charge operation with the switches 1203 and 1204, the time required for the circuit 1201 to retain original data again after the supply of the power supply voltage is restarted can be shortened.

In the circuit 1202, a signal retained by the capacitor 1208 is input to the gate of the transistor 1210. Therefore, after supply of the power supply voltage to the memory element 1200 is restarted, the signal retained by the capacitor 1208 can be converted into the one corresponding to the state (the on state or the off state) of the transistor 1210 to be read from the circuit 1202. Consequently, an original signal can be accurately read even when a potential corresponding to the signal retained by the capacitor 1208 varies to some degree.

By applying the above-described memory element 1200 to a memory device such as a register or a cache memory included in a processor, the loss of data in the memory device due to the stop of the supply of the power supply voltage can be prevented. Furthermore, shortly after the supply of the power supply voltage is restarted, the memory device can be returned to the same state as that before the power supply is stopped. Therefore, the power supply can be stopped even for a short time in the processor or one or a plurality of logic circuits included in the processor, resulting in lower power consumption.

Although the memory element 1200 is used in a CPU, the memory element 1200 can also be used in an LSI such as a digital signal processor (DSP), a custom LSI, or a programmable logic device (PLD), and a radio frequency identification (RF-ID).

<Display Device>

The following describes configuration examples of a display device according to one embodiment of the present invention.

Configuration Example

FIG. 23A is a top view of a display device according to one embodiment of the present invention. FIG. 23B illustrates a pixel circuit where a liquid crystal element is used for a pixel of a display device according to one embodiment of the present invention. FIG. 23C illustrates a pixel circuit where an organic EL element is used for a pixel of a display device according to one embodiment of the present invention.

The above-described transistor can be used as a transistor used for the pixel. Here, an example in which an n-channel transistor is used is shown. Note that a transistor manufactured through the same steps as the transistor used for the pixel may be used for a driver circuit. Thus, by using the above-described transistor for a pixel or a driver circuit, the display device can have high display quality and/or high reliability.

FIG. 23A illustrates an example of a top view of an active matrix display device. A pixel portion 5001, a first scan line driver circuit 5002, a second scan line driver circuit 5003, and a signal line driver circuit 5004 are provided over a substrate 5000 in the display device. The pixel portion 5001 is electrically connected to the signal line driver circuit 5004 through a plurality of signal lines and is electrically connected to the first scan line driver circuit 5002 and the second scan line driver circuit 5003 through a plurality of scan lines. Pixels including display elements are provided in respective regions divided by the scan lines and the signal lines. The substrate 5000 of the display device is electrically connected to a timing control circuit (also referred to as a controller or a control IC) through a connection portion such as a flexible printed circuit (FPC).

The first scan line driver circuit 5002, the second scan line driver circuit 5003, and the signal line driver circuit 5004 are formed over the substrate 5000 where the pixel portion 5001 is formed. Therefore, a display device can be manufactured at cost lower than that in the case where a driver circuit is separately formed. Furthermore, in the case where a driver circuit is separately formed, the number of wiring connections is increased. By providing the driver circuit over the substrate 5000, the number of wiring connections can be reduced. Accordingly, the reliability and/or yield can be improved.

[Liquid Crystal Display Device]

FIG. 23B illustrates an example of a circuit configuration of the pixel. Here, a pixel circuit which is applicable to a pixel of a VA liquid crystal display device, or the like is illustrated.

This pixel circuit can be applied to a structure in which one pixel includes a plurality of pixel electrodes. The pixel electrodes are connected to different transistors, and the transistors can be driven with different gate signals. Accordingly, signals applied to individual pixel electrodes in a multi-domain pixel can be controlled independently.

A gate wiring 5012 of a transistor 5016 and a gate wiring 5013 of a transistor 5017 are separated so that different gate signals can be supplied thereto. In contrast, a source or drain electrode 5014 functioning as a data line is shared by the transistors 5016 and 5017. The above-described transistor can be used as appropriate as each of the transistors 5016 and 5017. Thus, the liquid crystal display device can have high display quality and/or high reliability.

The shapes of a first pixel electrode electrically connected to the transistor 5016 and a second pixel electrode electrically connected to the transistor 5017 are described. The first pixel electrode and the second pixel electrode are separated by a slit. The first pixel electrode has a V shape and the second pixel electrode is provided so as to surround the first pixel electrode.

A gate electrode of the transistor 5016 is electrically connected to the gate wiring 5012, and a gate electrode of the transistor 5017 is electrically connected to the gate wiring 5013. When different gate signals are supplied to the gate wirings 5012 and 5013, operation timings of the transistors 5016 and 5017 can be varied. As a result, alignment of liquid crystals can be controlled.

Furthermore, a capacitor may be formed using a capacitor wiring 5010, a gate insulator functioning as a dielectric, and a capacitor electrode electrically connected to the first pixel electrode or the second pixel electrode.

One multi-domain pixel includes a first liquid crystal element 5018 and a second liquid crystal element 5019. The first liquid crystal element 5018 includes the first pixel electrode, a counter electrode, and a liquid crystal layer therebetween. The second liquid crystal element 5019 includes the second pixel electrode, a counter electrode, and a liquid crystal layer therebetween.

Note that a pixel circuit in the display device according to one embodiment of the present invention is not limited to that shown in FIG. 23B. For example, a switch, a resistor, a capacitor, a transistor, a sensor, a logic circuit, or the like may be added to the pixel circuit shown in FIG. 23B.

[Organic EL Display Device]

FIG. 23C illustrates another example of a circuit configuration of the pixel. Here, a pixel structure of a display device using an organic EL element is described.

In an organic EL element, by application of voltage to a light-emitting element, electrons are injected from one of a pair of electrodes included in the organic EL element and holes are injected from the other of the pair of electrodes, into a layer containing a light-emitting organic compound; thus, current flows. The electrons and holes are recombined, and thus, the light-emitting organic compound is excited. The light-emitting organic compound returns to a ground state from the excited state, thereby emitting light. Owing to such a mechanism, this light-emitting element is referred to as a current-excitation light-emitting element.

FIG. 23C illustrates an example of a pixel circuit. Here, one pixel includes two n-channel transistors. Note that the above-described transistor can be used as the n-channel transistors. Furthermore, digital time grayscale driving can be employed for the pixel circuit.

The configuration of the applicable pixel circuit and operation of a pixel employing digital time grayscale driving are described.

A pixel 5020 includes a switching transistor 5021, a driver transistor 5022, a light-emitting element 5024, and a capacitor 5023. A gate electrode of the switching transistor 5021 is connected to a scan line 5026, a first electrode (one of a source electrode and a drain electrode) of the switching transistor 5021 is connected to a signal line 5025, and a second electrode (the other of the source electrode and the drain electrode) of the switching transistor 5021 is connected to a gate electrode of the driver transistor 5022. The gate electrode of the driver transistor 5022 is connected to a power supply line 5027 through the capacitor 5023, a first electrode of the driver transistor 5022 is connected to the power supply line 5027, and a second electrode of the driver transistor 5022 is connected to a first electrode (a pixel electrode) of the light-emitting element 5024. A second electrode of the light-emitting element 5024 corresponds to a common electrode 5028. The common electrode 5028 is electrically connected to a common potential line provided over the same substrate.

As each of the switching transistor 5021 and the driver transistor 5022, the above-described transistor can be used as appropriate. In this manner, an organic EL display device having high display quality and/or high reliability can be provided.

The potential of the second electrode (the common electrode 5028) of the light-emitting element 5024 is set to be a low power supply potential. Note that the low power supply potential is lower than a high power supply potential supplied to the power supply line 5027. For example, the low power supply potential can be GND, 0 V, or the like. The high power supply potential and the low power supply potential are set to be higher than or equal to the forward threshold voltage of the light-emitting element 5024, and the difference between the potentials is applied to the light-emitting element 5024, whereby current is supplied to the light-emitting element 5024, leading to light emission. The forward voltage of the light-emitting element 5024 refers to a voltage at which a desired luminance is obtained, and includes at least forward threshold voltage.

Note that gate capacitance of the driver transistor 5022 may be used as a substitute for the capacitor 5023 in some cases, so that the capacitor 5023 can be omitted. The gate capacitance of the driver transistor 5022 may be formed between the channel formation region and the gate electrode.

Next, a signal input to the driver transistor 5022 is described. In the case of a voltage-input voltage driving method, a video signal which makes the driver transistor 5022 turned on or off is input to the driver transistor 5022. In order for the driver transistor 5022 to operate in a linear region, voltage higher than the voltage of the power supply line 5027 is applied to the gate electrode of the driver transistor 5022. Note that voltage higher than or equal to voltage which is the sum of power supply line voltage and the threshold voltage V_(th) of the driver transistor 5022 is applied to the signal line 5025.

In the case of performing analog grayscale driving, a voltage higher than or equal to a voltage which is the sum of the forward voltage of the light-emitting element 5024 and the threshold voltage V_(th) of the driver transistor 5022 is applied to the gate electrode of the driver transistor 5022. A video signal by which the driver transistor 5022 is operated in a saturation region is input, so that current is supplied to the light-emitting element 5024. In order for the driver transistor 5022 to operate in a saturation region, the potential of the power supply line 5027 is set higher than the gate potential of the driver transistor 5022. When an analog video signal is used, it is possible to supply current to the light-emitting element 5024 in accordance with the video signal and perform analog grayscale driving.

Note that in the display device according to one embodiment of the present invention, a pixel configuration is not limited to that shown in FIG. 23C. For example, a switch, a resistor, a capacitor, a sensor, a transistor, a logic circuit, or the like may be added to the pixel circuit shown in FIG. 23C.

In the case where the above-described transistor is used for the circuit shown in FIGS. 23A to 23C, the source electrode (the first electrode) is electrically connected to the low potential side and the drain electrode (the second electrode) is electrically connected to the high potential side. Furthermore, the potential of the first gate electrode may be controlled by a control circuit or the like and the potential described above as an example, e.g., a potential lower than the potential applied to the source electrode, may be input to the second gate electrode.

For example, in this specification and the like, a display element, a display device which is a device including a display element, a light-emitting element, and a light-emitting device which is a device including a light-emitting element can employ a variety of modes or can include a variety of elements. Examples of a display element, a display device, a light-emitting element, or a light-emitting device include an EL element (e.g., an EL element including organic and inorganic materials, an organic EL element, or an inorganic EL element), an LED (e.g., a white LED, a red LED, a green LED, or a blue LED), a transistor (a transistor which emits light depending on current), an electron emitter, a liquid crystal element, a display element using electronic ink, an electrophoretic element, a grating light valve (GLV), a plasma display panel (PDP), or a micro electro mechanical system (MEMS), a digital micromirror device (DMD), a digital micro shutter (DMS), an interferometric modulator display (IMOD) element, a MEMS shutter display element, an optical interference type MEMS display element, an electrowetting element, a piezoelectric ceramic display, or a carbon nanotube, which are display media whose contrast, luminance, reflectivity, transmittance, or the like is changed by electromagnetic action. Examples of a display device having an EL element include an EL display. Examples of a display device having an electron emitter include a field emission display (FED) and an SED-type flat panel display (SED: surface-conduction electron-emitter display). Examples of a display device having a liquid crystal element include a liquid crystal display (e.g., a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, or a projection liquid crystal display). Examples of a display device having electronic ink, or an electrophoretic element include electronic paper. In the case of a transflective liquid crystal display or a reflective liquid crystal display, some of or all of pixel electrodes function as reflective electrodes. For example, some or all of pixel electrodes are formed to contain aluminum, silver, or the like. In such a case, a memory circuit such as an SRAM can be provided under the reflective electrodes, leading to lower power consumption.

A coloring layer (also referred to as a color filter) may be used in order to obtain a full-color display device in which white light (W) for a backlight (e.g., an organic EL element, an inorganic EL element, an LED, or a fluorescent lamp) is used. As the coloring layer, red (R), green (G), blue (B), yellow (Y), or the like may be combined as appropriate, for example. With the use of the coloring layer, higher color reproducibility can be obtained than in the case without the coloring layer. In this case, by providing a region with the coloring layer and a region without the coloring layer, white light in the region without the coloring layer may be directly utilized for display. By partly providing the region without the coloring layer, a decrease in luminance due to the coloring layer can be suppressed, and 20% to 30% of power consumption can be reduced in some cases when an image is displayed brightly. Note that in the case where full-color display is performed using a self-luminous element such as an organic EL element or an inorganic EL element, elements may emit light of their respective colors R, G, B, Y, and W. By using a self-luminous element, power consumption can be further reduced as compared with the case of using the coloring layer in some cases.

<Module>

A display module using a semiconductor device according to one embodiment of the present invention is described below with reference to FIG. 24.

In a display module 8000 in FIG. 24, a touch panel 8004 connected to an FPC 8003, a cell 8006 connected to an FPC 8005, a backlight unit 8007, a frame 8009, a printed board 8010, and a battery 8011 are provided between an upper cover 8001 and a lower cover 8002. Note that the backlight unit 8007, the battery 8011, the touch panel 8004, and the like are not provided in some cases.

The semiconductor device according to one embodiment of the present invention can be used for the cell 8006, for example.

The shapes and sizes of the upper cover 8001 and the lower cover 8002 can be changed as appropriate in accordance with the sizes of the touch panel 8004 and the cell 8006.

The touch panel 8004 can be a resistive touch panel or a capacitive touch panel and may be formed to overlap with the cell 8006. A counter substrate (sealing substrate) of the cell 8006 can have a touch panel function. A photosensor may be provided in each pixel of the cell 8006 so that an optical touch panel is obtained. An electrode for a touch sensor may be provided in each pixel of the cell 8006 so that a capacitive touch panel is obtained.

The backlight unit 8007 includes a light source 8008. The light source 8008 may be provided at an end portion of the backlight unit 8007 and a light diffusing plate may be used.

The frame 8009 may protect the cell 8006 and also function as an electromagnetic shield for blocking electromagnetic waves generated by the operation of the printed board 8010. The frame 8009 may function as a radiator plate.

The printed board 8010 has a power supply circuit and a signal processing circuit for outputting a video signal and a clock signal. As a power source for supplying power to the power supply circuit, an external commercial power source or a power source using the battery 8011 provided separately may be used. The battery 8011 can be omitted in the case of using a commercial power source.

The display module 8000 can be additionally provided with a member such as a polarizing plate, a retardation plate, or a prism sheet

<Electronic Device>

The semiconductor device according to one embodiment of the present invention can be used for display devices, personal computers, or image reproducing devices provided with recording media (typically, devices which reproduce the content of recording media such as digital versatile discs (DVDs) and have displays for displaying the reproduced images). Other examples of electronic devices that can be equipped with the semiconductor device according to one embodiment of the present invention are mobile phones, game machines including portable game consoles, portable data appliances, e-book readers, cameras such as video cameras and digital still cameras, goggle-type displays (head mounted displays), navigation systems, audio reproducing devices (e.g., car audio systems and digital audio players), copiers, facsimiles, printers, multifunction printers, automated teller machines (ATM), and vending machines. FIGS. 25A to 25F illustrate specific examples of these electronic devices.

FIG. 25A illustrates a portable game console including a housing 901, a housing 902, a display portion 903, a display portion 904, a microphone 905, a speaker 906, an operation key 907, a stylus 908, and the like. Although the portable game console in FIG. 25A has the two display portions 903 and 904, the number of display portions included in a portable game console is not limited to this.

FIG. 25B illustrates a portable data terminal including a first housing 911, a second housing 912, a first display portion 913, a second display portion 914, a joint 915, an operation key 916, and the like. The first display portion 913 is provided in the first housing 911, and the second display portion 914 is provided in the second housing 912. The first housing 911 and the second housing 912 are connected to each other with the joint 915, and the angle between the first housing 911 and the second housing 912 can be changed with the joint 915. An image on the first display portion 913 may be switched depending on the angle between the first housing 911 and the second housing 912 at the joint 915. A display device with a position input function may be used as at least one of the first display portion 913 and the second display portion 914. Note that the position input function can be added by providing a touch panel in a display device. Alternatively, the position input function can be added by provision of a photoelectric conversion element called a photosensor in a pixel portion of a display device.

FIG. 25C illustrates a laptop personal computer, which includes a housing 921, a display portion 922, a keyboard 923, a pointing device 924, and the like.

FIG. 25D illustrates an electric refrigerator-freezer including a housing 931, a door for a refrigerator 932, a door for a freezer 933, and the like.

FIG. 25E illustrates a video camera, which includes a first housing 941, a second housing 942, a display portion 943, operation keys 944, a lens 945, a joint 946, and the like. The operation keys 944 and the lens 945 are provided for the first housing 941, and the display portion 943 is provided for the second housing 942. The first housing 941 and the second housing 942 are connected to each other with the joint 946, and the angle between the first housing 941 and the second housing 942 can be changed with the joint 946. Images displayed on the display portion 943 may be switched in accordance with the angle at the joint 946 between the first housing 941 and the second housing 942.

FIG. 25F illustrates an ordinary vehicle including a car body 951, wheels 952, a dashboard 953, lights 954, and the like.

<Electronic Device with Curved Display Region or Curved Light-Emitting Region>

Electronic devices with a curved display region or a curved light-emitting region according to one embodiment of the present invention are described below with reference to FIGS. 26A1, 26A2, 26A3, 26B1, 26B2, 26C1, and 26C2. Here, information devices, in particular, portable information devices (portable devices) are described as examples of the electronic devices. The portable information devices include, for example, mobile phone devices (e.g., phablets and smartphones) and tablet terminals (slate PCs).

FIG. 26A1 is a perspective view illustrating an external shape of a portable device 1300A. FIG. 26A2 is a top view illustrating the portable device 1300A. FIG. 26A3 illustrates a usage state of the portable device 1300A.

FIGS. 26B1 and 26B2 are perspective views illustrating the outward form of a portable device 1300B.

FIGS. 26C1 and 26C2 are perspective views illustrating the outward form of a portable device 1300C.

<Portable Device>

The portable device 1300A has one or more functions of a telephone, email creating and reading, notebook, information browsing, and the like.

A display portion of the portable device 1300A is provided along a plurality of surfaces of a housing. For example, the display portion may be provided by placing a flexible display device along the inside of the housing. Thus, text data, image data, or the like can be displayed on a first region 1311 and/or a second region 1312.

For example, images used for three operations can be displayed on the first region 1311 (see FIG. 26A1). Furthermore, text data and the like can be displayed on the second region 1312 as indicated by dashed rectangles in the drawing (see FIG. 26A2).

In the case where the second region 1312 is on the upper portion of the portable device 1300A, a user can easily see text data or image data displayed on the second region 1312 of the portable device 1300A while the portable device 1300A is placed in a breast pocket of the user's clothes (see FIG. 26A3). For example, the user can see the phone number, name, and the like of the caller of an incoming call, from above the portable device 1300A.

The portable device 1300A may include an input device or the like between the display device and the housing, in the display device, or over the housing. As the input device, for example, a touch sensor, a light sensor, or an ultrasonic sensor may be used. In the case where the input device is provided between the display device and the housing or over the housing, a touch panel may be, for example, a matrix switch type, a resistive type, an ultrasonic surface acoustic wave type, an infrared type, electromagnetic induction type, or an electrostatic capacitance type. In the case where the input device is provided in the display device, an in-cell sensor, an on-cell sensor, or the like may be used.

Note that the portable device 1300A can be provided with a vibration sensor or the like and a memory device that stores a program for shifting a mode into an incoming call rejection mode based on vibration sensed by the vibration sensor or the like. Thus, the user can shift the mode into the incoming call rejection mode by tapping the portable device 1300A over his/her clothes to apply vibration.

The portable device 1300B includes a display portion including the first region 1311 and the second region 1312 and a housing 1310 which supports the display portion.

The housing 1310 has a plurality of bend portions, and the longest bend portion in the housing 1310 is between the first region 1311 and the second region 1312.

The portable device 1300B can be used with the second region 1312 provided along the longest bend portion facing sideward.

The portable device 1300C includes a display portion including the first region 1311 and the second region 1312 and a housing 1310 which supports the display portion.

The housing 1310 has a plurality of bend portions, and the second longest bend portion in the housing 1310 is between the first region 1311 and the second region 1312.

The portable device 1300C can be used with the second region 1312 facing upward.

This application is based on Japanese Patent Application serial no. 2014-015551 filed with the Japan Patent Office on Jan. 30, 2014, the entire contents of which are hereby incorporated by reference. 

What is claimed is:
 1. A method of manufacturing a semiconductor device comprising a semiconductor, a first conductor, a second conductor, a third conductor, and an insulator, the semiconductor comprising: a first region in contact with the first conductor; a second region in contact with the second conductor; and a third region in contact with the insulator, wherein the third conductor and the semiconductor overlap with each other with the insulator therebetween, wherein the first region and the third region do not overlap with each other, and wherein the second region and the third region do not overlap with each other, the method comprising the steps of: selectively growing the first conductor over the first region; and selectively growing the second conductor over the second region.
 2. A method of manufacturing a semiconductor device, comprising the steps of: forming a semiconductor over a first insulator; forming a second insulator over the semiconductor; forming a first conductor over the second insulator; forming a second conductor and a third insulator by etching part of the first conductor and part of the second insulator respectively, wherein the second conductor overlaps with the semiconductor with the third insulator therebetween; adding an impurity to the semiconductor with the second conductor as a mask; forming a fourth insulator over the semiconductor and the second conductor; anisotropically etching the fourth insulator to form a fifth insulator on a side surface of the second conductor and to expose an upper surface of the semiconductor; and selectively growing a conductor over the exposed upper surface of the semiconductor.
 3. The method of manufacturing a semiconductor device, according to claim 2, comprising further the step of: etching an exposed region of the first insulator to form a region having a small thickness in the first insulator at the same time as the anisotropically etching.
 4. The method of manufacturing a semiconductor device, according to claim 2, wherein the impurity is added by an ion implantation method.
 5. The method of manufacturing a semiconductor device, according to claim 2, wherein the impurity is added by an ion implantation method using a cluster ion.
 6. The method of manufacturing a semiconductor device, according to claim 2, wherein the impurity comprises silicon, and wherein the conductor is selectively grown by a chemical vapor deposition method using a gas comprising tungsten.
 7. The method of manufacturing a semiconductor device, according to claim 6, wherein the gas comprising tungsten comprises a tungsten hexafluoride gas or a monosilane gas.
 8. The method of manufacturing a semiconductor device, according to claim 2, wherein the impurity comprises titanium, and wherein the conductor is selectively grown by a chemical vapor deposition method using a gas comprising aluminum.
 9. The method of manufacturing a semiconductor device, according to claim 8, wherein the gas comprising aluminum comprises a diethylaluminium hydride gas.
 10. A method of manufacturing a semiconductor device, comprising the steps of: forming a semiconductor over a first insulator; forming a second insulator over the semiconductor; forming a first conductor over the second insulator; forming a second conductor by etching part of the first conductor, the second conductor overlapping with the semiconductor with the second insulator therebetween; forming a third insulator over the second insulator and the second conductor; adding an impurity to the semiconductor with the second conductor as a mask; forming a fourth insulator over the third insulator; anisotropically etching the third insulator and the fourth insulator to form a fifth insulator on a side surface of the second conductor and to expose an upper surface of the semiconductor, wherein an exposed portion of the second insulator is etched by the anisotropically etching; and selectively growing a conductor over the exposed upper surface of the semiconductor.
 11. The method of manufacturing a semiconductor device, according to claim 10, comprising further the step of: etching an exposed region of the first insulator to form a region having a small thickness in the first insulator at the same time as the anisotropically etching.
 12. The method of manufacturing a semiconductor device, according to claim 10, wherein the impurity is added by an ion implantation method.
 13. The method of manufacturing a semiconductor device, according to claim 10, wherein the impurity is added by an ion implantation method using a cluster ion.
 14. The method of manufacturing a semiconductor device, according to claim 10, wherein the impurity comprises silicon, and wherein the conductor is selectively grown by a chemical vapor deposition method using a gas comprising tungsten.
 15. The method of manufacturing a semiconductor device, according to claim 14, wherein the gas comprising tungsten comprises a tungsten hexafluoride gas or a monosilane gas.
 16. The method of manufacturing a semiconductor device, according to claim 10, wherein the impurity comprises titanium, and wherein the conductor is selectively grown by a chemical vapor deposition method using a gas comprising aluminum.
 17. The method of manufacturing a semiconductor device, according to claim 16, wherein the gas comprising aluminum comprises a diethylaluminium hydride gas.
 18. A method of manufacturing a semiconductor device, comprising the steps of: forming a semiconductor over an insulator; forming a gate insulator over the semiconductor; forming a gate electrode over the gate insulator; forming side walls on side surfaces of the gate electrode; forming conductive layers on exposed upper surfaces of the semiconductor after forming the side walls; forming an insulating layer over the semiconductor, the gate electrode and the conductive layers; forming a contact hole in the insulating layer so that one of the conductive layers is exposed in the contact hole; and forming a second conductive layer in the contact hole.
 19. The method of manufacturing a semiconductor device, according to claim 18, comprising further the step of: etching an exposed region of the insulator to form a region having a small thickness in the insulator at the same time as forming the side walls.
 20. The method of manufacturing a semiconductor device, according to claim 18, wherein the conductive layers are selectively grown by a chemical vapor deposition method using a gas comprising tungsten.
 21. The method of manufacturing a semiconductor device, according to claim 20, wherein the gas comprising tungsten comprises a tungsten hexafluoride gas or a monosilane gas.
 22. The method of manufacturing a semiconductor device, according to claim 18, wherein the conductive layers are selectively grown by a chemical vapor deposition method using a gas comprising aluminum.
 23. The method of manufacturing a semiconductor device, according to claim 22, wherein the gas comprising aluminum comprises a diethylaluminium hydride gas. 